Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
154 Design Guide
R
10.3.4. CLK33 Clock Group
The driver is the clock synthesizer 33-MHz clock output buffer and the receiver is the 33-MHz clock
input buffer at the Intel ICH3-M, FWH, Glue Chip, and SIO. Note that the goal is to have minimal (~ 0)
skew between the clocks within this group, and also minimal (~ 0) skew between the clocks of this group
and that of group CLK66.
Figure 85. Topology for CLK33
A
R1
Clock
Driver
ICH2, SIO,
Glue Chip,
FWH
B
Table 53. CLK33 Routing Guidelines
Parameter Routing Guidelines
Clock Group CLK33
Topology Point to point
Reference Plane Ground Referenced (Contiguous over entire Length)
Characteristic Trace Impedance (Zo) 55 Ohms ± 15%
Trace Width 4 mils
Trace Spacing 20 mils
Spacing to other traces 20 mils
Trace Length – A Same as CLK66 Trace A
This trace must be exactly length matched to CLK66 Trace A
Trace Length – B Same as CLK66 Trace B
This trace must be exactly length matched to CLK66 Trace B
Resistor R1 = 33 ohms ±1%
Skew Requirements Should have minimal (~ 0) skew between the clocks within this group, and
also minimal (~ 0) skew between the clocks of this group and that of
group CLK66
.
10.3.5. CLK14 Clock Group
The driver is the clock synthesizer 14.318-MHz clock output buffer and the receiver is the 14.318-MHz
clock input buffer at the ICH3-M and SIO. Note that the clocks within this group should have minimal
skew (~ 0) between each other, however each of the clocks in this group are asynchronous to clocks of
any other group.