Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel

Pentium

4 Processor-M and Intel

845MP/845MZ Chipset Platform

Design Guide 163

the voltage at the base of the PNP transistor. By connecting the emitter of the NPN transistor to the 1.8 V

plane, current will not flow from the 3.3-V supply into 1.8-V plane when the 1.8-V plane reaches 1.8 V.

Figure 91. Example 1.8-V/3.3-V Power Sequencing Circuit

PNP

NPN

220

470

+3.3V

+1.8V

When analyzing systems that may be "marginally compliant" to the 2 V Rule, please pay close attention

to the behavior of the ICH3-M's RSMRST#, PWROK, and LAN_RST# in ICH3-M signals, since these

signals control internal isolation logic between the various power planes:

• RSMRST# controls isolation between the RTC well and the Resume wells

• PWROK controls isolation between the Resume wells and Main wells

• LAN_RST# controls isolation between the LAN wells and the Resume wells (applies only to ICH3-

If one of these signals goes high while one of its associated power planes is active and the other is not, a

leakage path will exist between the active and inactive power wells. This could result in high, possibly

damaging, internal currents.

11.4.2.2. 3.3-V/V5REF and 3.3SUS/V5REF_SUS Sequencing

V5REF is the reference voltage for 5-V tolerance on inputs to the ICH3-M. V5REF must be powered up

before VCC3_3, or after VCC3_3 within 0.7V. Also, V5REF must power down after VCC3_3, or before

VCC3_3 within 0.7 V. The rule must be followed in order to ensure the safety of the ICH3-M. If the rule

is violated, internal diodes will attempt to draw power sufficient to damage the diodes from the VCC3_3

rail. Figure 92 shows a sample implementation of how to satisfy the V5REF/3.3V sequencing rule. This

rule also applies to the standby rails, but in most platforms, the VCCSUS3_3 rail is derived from the

VCCSUS5 rail and therefore, the VCCSUS3_3 rail will always come up after the VCCSUS5 rail. As a

result, V5REF_SUS will always be powered up before VCCSUS3_3. In platforms that do not derive the

VCCSUS3_3 rail from the VCCSUS5 rail, this rule must be comprehended in the platform design.