Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
Design Guide 173
R
11.7.3. Intel 845MP/845MZ Chipset DDR Reference Board Power
Delivery
Figure 96 shows the power delivery architecture for the Intel 845MP/845MZ Chipset DDR memory
subsystem. This power delivery example provides support for the suspend-to-RAM (STR) and the full
Power-on State.
Figure 96. Intel 845MP/845MZ Chipset DDR Power Delivery Example
MCH-M
Memory
Interface
VCCSM:2.50V
1.9A , 4.75W
SDREF:
1.25V,50uA
VDD & VDDQ:
2.5V,5.9A, 14.8W
VTT: 1.25V
TERM RES
VREF:
1.25V,1mA
+VDC
DDR VR
Vout = 1.25V,
DDR VR
Vout = 2.5V
SMRCOMP:
1.25V,80mA
VREF IN
VREF DIVIDER AND
BUFFER CIRCUIT
SO-DIMM
NOTES:
1. Designer must follow following recommendations.
2. VDD & VDDQ (2.5 V) must stay on to drive CKE signals in S3 state.
3. During S3 state VTT and SMRCOMP can be turned off.
4. VTT must have smooth soft start to prevent glitches.
5. VREF(DDR) & SDREF(MCH-M) must stay on to acknowledge the state of CKE signals in S3 state.
Following requirements must be met in order to turn off DDR Vtt in the S3 power state:
MCH-M VCCSM (2.5 V) and SDREF must stay on to drive CKE signals in S3. DDR Vtt must have a
smooth soft start to prevent glitches that can affect CKE pins being driven low. DDR Vtt must be stable
and within voltage tolerance specification before ICH deasserts reset (PCIRST) to the MCH-M.
Optional: Vtt to SMRCOMP can be off in S3 following the same above requirements. Please note MCH-
M will enable a weak pull-up when reset is asserted, so the command signals should all be high during
S3.
11.7.4. DDR Reference Voltage
The table below has grouped the voltage and current specifications together for each the MCH-M,
memory and termination voltage. There are 7 voltages specified here for a DDR VR system. Although,
there are only 2 unique voltage regulators for 2.5 V and 1.25 V nominal, each specific power rail
described here has a unique specification. Described below are the memory components themselves first