Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
Design Guide 193
R
12.9. MCH-M Signals
Table 77. Processor System Bus Signals
MCH-M – Processor System Bus (PSB) Signals
Signal System
Pull-up/Pull-down
Ω
ΩΩ
Ω Notes 9
99
9
H_D#[63:0],
H_A#[31:3],
H_REQ#[4:0],
H_RS#[2:0]
Route all signals between processor and MCH-
M with board trace impedance
H_RESET# Route all signals between processor and MCH-
M with 55
Ω ± 1% trace impedance; Also drives
H_RESETX w/ 0
Ω series damping
H_ADS#,
H_BNR#,
H_BPRI#,
H_DBSY#,
H_DEFER#,
H_DRDY#,
H_HIT#,
H_HITM#,
H_LOCK#,
H_TRDY#
Route all signals between processor and MCH-
M with 55
Ω ± 1% trace impedance
H_XRCOMP
H_YRCOMP
Connect to GND 24.9 Ω ±1% Referencing a 50-Ω buffer impedance
SCK6/CLK6,
SCK#6/CLK7,
SCK7/CLK10,
SCK#7/CLK11,
SCK8/CLK9,
SCK#8/CLK8
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
HXSWING
HYSWING
NOTE: Please refer to Customer Reference Board schematic for SCKE[3:0] connection. Also SCS#[5:4] are NC.
Intel does not support SCS[5:4].