Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
Design Guide 207
R
12.18. GPIO
Table 103. GPIO Recommendation
Checklist Items Recommendations Reason/Impact
GPIO Balls
GPIO[7, 5:0]:
•
These balls are in the Main Power Well. Pull-
ups must use the V
CC
3_3 plane.
• Unused core well inputs must be pulled up to
V
CC
3_3.
• GPIO[1:0] can be used as REQ[B:A]#.
• GPIO[1] can be used as PCI REQ[5]#.
• GPIO[5:2] can be used as PIRQ[H:E]#.
• These signals are 5V tolerant
GPIO[8] & [13:11]:
•
These balls are in the Resume Power Well.
Pull-ups go to V
CC
Sus3_3 plane.
• Unused resume well inputs must be pulled up to
V
CC
Sus3_3.
• These are the only GPIs that can be used as
ACPI compliant wake events.
• These signals are not 5V tolerant.
• GPIO[11] can be used as SMBALERT#.
GPIO[24:16]:
•
Fixed as output only. Can be left NC.
• In Main Power Well (V
CC
3_3).
• GPIO[22] is open drain.
• GPIO[17:16] can be used as GNT[B:A]#.
• GPIO[17] can be used as PCI GNT[5]#.
• GPIO[18] / STP_PCI#
• GPIO[19] / SLP_S1#
• GPIO[20] / STP_CPU#
• GPIO[21] can be used as C3_STAT#
• GPIO[22] / CPUPERF#
• GPIO[23] / SSMUXSEL
GPIO[28,27,25,24]:
•
I/O balls. Default as outputs. Can be left NC.
• GPIO[24]/CLKRUN#
• From resume power well (V
CC
Sus3_3).
• GPIO[24] / CLKRUN#
†
(Note: use pull-up to
V
CC
3_3 if this signal is pulled-up)
GPIO[43:32]:
•
I/O balls. From main power well (V
CC
3_3).
Default as outputs when enabled as GPIOs.
Ensure ALL unconnected signals are
OUTPUTS ONLY!
These are the only GPI signals in the
resume well with associated status bits
in the GPE1_STS register.
Main power well GPIO are 5 V tolerant,
except for GPIO[43:32]. Resume power
well GPIOs are not 5 V tolerant. Muxed
pins with Power Management
functionality are used for their respective
power management functions