Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel

Pentium

4 Processor-M and Intel

845MP/845MZ Chipset Platform

Design Guide 21

• AGTL+ host bus with integrated termination supporting 32-bit host addressing

• 1.5-V AGP interface with 4x SBA/data transfer and 2x/4x fast write capability

• 8-bit, 66-MHz,, 4x hub interface to the Intel ICH3-M

1.4.1.1. Processor System Bus Support

• AGTL+ bus driver technology (gated AGTL+ receivers for reduced power)

• Supports 32-bit AGTL+ bus addressing (no support for 36-bit address extension)

• Supports Uniprocessor (UP) systems

• 400 MT/s PSB support

• Optimized for Mobile Intel Pentium 4 Processor-M in 478-pin Micro-FCPGA package

• 12 deep in-order queue

• Supports in-order and dynamic deferred transactions

• Low Vtt

1.4.1.2. Integrated System Memory DRAM Controller

• Supports up to 2 SO-DIMMs

• Up to 1 GB using 64-Mb, 128-Mb, 256-Mb, 512-Mb technology

• 200/266 MHz DDR interface

• 64-bit data interface

• PC2100 and PC1600 system memory interface

• Supports x16 DDR device widths with Dynamic Powerdown Support for suspend to RAM (STR)

and S3

• Supports up to 16 simultaneous open pages

• Refresh Mechanism: CAS-before-RAS only

• Support for DIMM Serial Presence Detect (SPD) scheme via SMBus interface STR power

management support via self refresh mode using CKE

1.4.1.2.1. Accelerated Graphics Port (AGP) Interface

• Supports AGP 2.0 data transfers

• Supports a single AGP (4X/2X/1X) device (either via a connector or on the motherboard)

• AGP 1.5-V Connector support only

• Synchronously coupled to the host with 1:2 clock ratio

• High priority access support

• Delayed transaction support for AGP reads that cannot be serviced immediately

•

AGP semantic traffic to the DRAM is not snooped on the PSB and is therefore not coherent with the

CPU caches