Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
22 Design Guide
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AGP BUSY protocol.
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AGP Clamping and sense amp control
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Supports 32-deep AGP address queue.
1.4.1.3. Packaging/Power
• 593-pin, FC-BGA package
• 1.5 V (±5%) core and mixed 3.3 V, 1.5 V, 1.8 V, and AGTL+ I/O
1.4.1.4. I/O Controller Hub (ICH3-M)
ICH3-M provides the I/O subsystem with access to the rest of the system:
• Upstream Accelerated Hub Architecture interface at 266 MB/s for access to the MCH-M
• PCI 2.2 interface (6 PCI Req/Grant Pairs)
• Bus Master IDE controller (supports Ultra ATA 100/66/33)
• USB 1.1 Controller
• SMBus Controller
• FWH Interface
• LPC Interface
• AC’97 2.1 Interface
• Integrated System Management Controller
• Alert-On-LAN
• IRQ Controller
1.4.1.4.1. Packaging/Power
• 421 BGA
• 3.3-V core and 1.8-V and 3.3-V standby
1.4.1.5. Firmware Hub (FWH)
• An integrated hardware Random Number Generator (RNG)
• Register-based locking
• Hardware-based locking
• 5 GPIs
1.4.1.5.1. Packaging/Power
• 32-Pin PLCC
• 3.3-V core and 3.3 V/12 V for fast programming
• Register-based locking
1.4.2. Bandwidth Summary
Table 3 lists the bandwidths of critical 845MP/845MZ chipset platform interfaces.