Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
CK-408
No Stuff
1
200Mhz Host CLK
1
SEL0
100Mhz Host CLK
133Mhz Host CLK
0
0
SEL1
0 66Mhz Host CLK
0
1
FUNCTION
1
475 1%
1
MULT
1.0 VOLTS
CK408 CLOCK SWING CONFIG
R331
0.7 VOLTS
0
221 1%
Note:
1) CPU[2:0] needs to be running in C3, C4
2) PCIF2 should be the free-running PCI
clock
Place 0ohm
near
crystal.
Place crystal within 500
mils of CK_TITAN
No stuff;
caps are
internal to
CK-408.
Measurement Point
Used for D3 Hot
Correct CK408 IPN is:
A62115-001
Only need the AND gate if
S1M is supported
CK-408
14 42
845MP/MZ Platformm
Title
Sheet of
Project:
+V3SA_CLK
CLK_REF0
+VDD3S_CLK
CK408_SEL2
CK408_SEL0
CK_IREF
CK408_SEL1
XTAL_OUT
XTAL_IN
VDD5_48Mhz
CK408PWRDN#
CK408PWRDN#
CLK_ITP 5
CLK_ITP# 5
CLK_PLD4
+V3.3S_CLKSRC
+V3.3S_CLKSRC
+V3.3S4,5,6,9,10,17,19,23,28,29,30,31,32,33,36,37,40
+V3.3S_CLKSRC
+V3.3S_CLKSRC
CLK_AGP_SLOT 9
CLK_ICH66 8,15
CLK_ICHPCI 15
CLK_PCI_PORT80 30
CLK_PCI_SLOT3 19
CLK_PCI_SLOT2 18
CLK_PCI_SLOT1 18
CLK_DOCKPCI 20
CLK_FWHPCI 28
CLK_SIOPCI 31
CLK_SMCPCI 29
CLK_LPCPCI 34
CLK_ICH48 16
CLK_LPC14 34
CLK_SIO14 31
CLK_ICH14 16
CLK_ITP_CPU
3
CLK_ITP_CPU# 3
CLK_MCH_BCLK 7
CLK_MCH_BCLK# 7
SMB_DATA10,15,20,22
H_BSEL0
3
H_BSEL1
3
PM_STPPCI#16,34
PM_STPCPU#16,34,36,37
VR_PWRGD_CK408#
36
SMB_CLK10,15,20,22
CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3
CLK_MCH66 6
PM_SLP_S1#16,24,34,40
+V3.3
17,19,21,24,27,29,34,36,40
PM_SLP_S3#16,21,29,34,39,40
R42
1K
R68 33
C437
0.1UF
R52
0
RP8D 33
4 5
R470
NO_STUFF_0
C431
1UF
12
R41 33
R62
NO_STUFF_0
R37
NO_STUFF_0
R330 10K
C439
0.1UF
RP7C 33
3 6
C115
22UF
R82 33
R332
1K
C113
22UF
C429
0.1UF
R43
1K
C433
0.1UF
C542NO_STUFF_10pF
R45 NO_STUFF_0
RP9B 33
2 7
C432
0.1UF
U60
74AHC1G08
1
2
4
53
C45 NO_STUFF_10pF
R58 33
R51
0
RP7A 33
1 8
C128
22UF
R84
NO_STUFF_0.01_1%
12
R44
NO_STUFF_330
C60 NO_STUFF_10pF
R72 33
FB22
300ohm@100MHz
1 2
R78
NO_STUFF_54.9_1%
R77 33
RP9C 33
3 6
C46
NO_STUFF_10pF
C71 NO_STUFF_10pF
R328 0
R39
NO_STUFF_0
C89 NO_STUFF_10pF
Q5
NO_STUFF_BAR43
C61 NO_STUFF_10pF
RP16B33
2 7
C438
0.1UF
R389 33
C68
NO_STUFF_10pF
C118
NO_STUFF_10pF
R63
NO_STUFF_0
C77 NO_STUFF_10pF
R65
NO_STUFF_54.9_1%
RP9D 33
4 5
C59 NO_STUFF_10pF
C75 NO_STUFF_10pF
R40 33
C105 NO_STUFF_10pF
C91 NO_STUFF_10pF
R54 33
J18
1 2
R59
NO_STUFF_54.9_1%
R329 NO_STUFF_10K
C98 NO_STUFF_10pF
R69
NO_STUFF_54.9_1%
C81 NO_STUFF_10pF
C110
NO_STUFF_10pF
C101 NO_STUFF_10pF
C109
NO_STUFF_10pF
R64 33
RP8A 33
1 8
J19
NO_STUFF_SMA CON
35
4
1
2
FB21
300ohm@100MHz
1 2
RP16C33
3 6
R55
NO_STUFF_54.9_1%
C435
0.1UF
R49 0
C67 NO_STUFF_10pF
R38 33
RP8B 33
2 7
C430
0.1UF
FB20
300ohm@100MHz
1 2
Y2
14.318MHZ
21
Q7
NO_STUFF_BAR43
RP16D33
4 5
U16
CK-408
10
11
12
13
16
17
18
7
4
6
261
27
5
45
8
44
9
49
14
48
20
52
19
51
32
24
31
23
37
22
46
21
36
50
39
2
38
47
56
3
42
40
55
54
43
25
34
53
28
29
30
33
35
15
41
PCI0
PCI1
PCI2
PCI3
PCI4
PCI5
PCI6
PCIF2
VSS0
PCIF1
VDDAVDD0
VSSA
PCIF0
CPU2
VDD1
CPU2#
VSS1
CPU1
VDD2
CPU1#
VSS2
CPU0
VDD3
CPU0#
VDD4
66INPUT
VSS3
66BUF2
VDD5
66BUF1
VDD6
66BUF0
VSS4
VDD7
USB
XTAL_IN
DOT
VSS5
REF
XTAL_OUT
IREF
SEL2
SEL1
SEL0
MULT0
PWRDWN#
PCI_STOP#
CPU_STOP#
VTT_PWRGD#
SDATA
SCLOCK
3V66_0
3V66_1/VCH
VSS6
VSSIREF
R331
475_1%
C427
0.1UF
RP8C 33
3 6
R75
NO_STUFF_54.9_1%
RP7B 33
2 7
C86
0.1UF
224
Design Guide