Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
24 Design Guide
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2. General Design Considerations
This section documents motherboard layout and routing guidelines for Intel 845MP/845MZ platforms.
This section does not discuss the functional aspects of any bus, or the layout guidelines for an add-in
device.
If the guidelines listed in this document are not followed, it is very important that thorough signal
integrity and timing simulations are completed for each design. Even when the guidelines are followed,
Intel recommends that critical signals be simulated to ensure proper signal integrity and flight time. Any
deviation from the guidelines should be simulated.
The trace impedance typically noted (i.e. 55 Ω ± 15%) is the “nominal” trace impedance for a 5-mil wide
external trace and a 4-mil wide internal trace. That is, the impedance of the trace when not subjected to
the fields created by changing current in neighboring traces. When calculating flight times, it is important
to consider the minimum and maximum impedance of a trace that is based on the switching of
neighboring traces. Using wider spaces between the traces can minimize this trace-to-trace coupling. In
addition, these wider spaces reduce settling time.
Coupling between two traces is a function of the coupled length, the distance separating the traces, the
signal edge rate, and the degree of mutual capacitance and inductance. In order to minimize the effects of
trace-to-trace coupling, the routing guidelines documented in this section should be followed.
2.1. Nominal Board Stackup
The Intel 845MP/845MZ Chipset platform requires a board stackup yielding a target impedance of 55 Ω
± 15% with a 5-mil wide external trace and a 4-mil wide internal trace width for all interfaces.