Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
FLOPPY CONNECTOR
INFRARED PORT
Note: FORCEOFF# overrides FORCEON.
PARALLEL PORT
Caps must be placed
as close as possible to
pins 1,2
R2OUTB is enabled even in suspend.
SER_RIA# is routed to allow the system to
wake up in Suspend To RAM.
SERIAL PORT
Floppy, Parallel, Serial, and IR Ports
32 42
845MP/MZ Platformm
Title
Sheet of
Project:
PPT_L_PD1
PPT_L_PD4
PPT_L_PD6
PPT_L_PD2
PPT_L_SLIN#
PPT_L_PD7
PPT_L_BUSY/WAIT#
PPT_L_ACK#
PPT_L_PD5
PPT_L_PD0
PPT_L_PE
PPT_L_SLCT
PPT_L_PNF#
PPT_L_INIT#
PPT_L_ERR#
PPT_L_AFD#/DSTRB#
PPT_L_STB#/WRITE#
PPT_L_PD3
SERBUF_C2-
SERBUF_RIA
SER_RIA
SERBUF_C1-
SERBUF_V+
SERBUF_V-
SER_ON
SERBUF_DTRA
SERBUF_C2+
SERBUF_C1+
SERBUF_SINA#
SERBUF_DCDA
SERBUF_CTSA
SERBUF_RTSA
SERBUF_DSRA
SERBUF_SOUTA#
SERPRT_RIA
SERPRT_DCDA
SERPRT_SINA#
SERPRT_CTSA
SERPRT_DSRA
SERPRT_SOUTA#
SERPRT_DTRA
SERPRT_RTSA
PM_RI#
16,21,22,34
+V3.3S_IR
+V5S4,9,17,19,20,24,31,33,35,36,37,40
+V3.3ALWAYS 9,16,17,18,19,24,25,26,29,33,34,39,40
+V3.3S
4,5,6,9,10,14,17,19,23,28,29,30,31,33,36,37,40
+V3.3S4,5,6,9,10,14,17,19,23,28,29,30,31,33,36,37,40
PPT_PD631
PPT_PD031
PPT_PD431
PPT_PD531
PPT_PD331
PPT_PD231
PPT_PD731
PPT_PD131
IR_SEL31
IR_MD131
IR_MD031
FLP_MTR0# 31
FLP_HDSEL# 31
FLP_WGATE# 31
FLP_DR0# 31
FLP_STEP# 31
FLP_DIR# 31
FLP_WDATA# 31
FLP_DENSEL# 31
FLP_DRATE0 31
PPT_SLCT31
PPT_ERR#31
PPT_ACK#31
PPT_PE31
PPT_BUSY/WAIT#31
PPT_PNF#31
IR_RXD31
SER_CTSA#20,31
SER_SINA20,31
SER_RIA#20,31
SER_DSRA#20,31
SER_DCDA#20,31
FLP_TRK0# 31
FLP_RDATA# 31
FLP_DSKCHG# 31
FLP_INDEX# 31
FLP_WP# 31
PPT_SLIN#/ASTRB#31
PPT_STB#/WRITE#31
PPT_AFD#/DSTRB#31
PPT_INIT#31
IR_TXD31
SER_RTSA#20,31
SER_DTRA#20,31
SER_SOUTA20,31
SER_EN
16
FB11C
60OHM@100MHZ
3 6
R9
2.2
FB10B
2 7
FB6C
60OHM@100MHZ
3 6
FB10D
4 5
C26
0.1UF
U1
HSDL-3600#017
10
9
8
7
6
5
4
3
2
1 11
LEDA
TXD
RXD
GND
NC
MOD1
MOD0
FIR_SEL
AGND
VDD MNT
GND0
GND1
J1
SERIAL
5
9
4
8
3
7
2
6
1
10
11
FB8A
1 8
C7
0.1UF
FB6D
4 5
C24
0.1UF
GND0
GND1
GND2
J4
PARALLEL
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
26
27
28
R423
1K
FB9C
60OHM@100MHZ
3 6
FB5C
60OHM@100MHZ
3 6
FB9B
2 7
FB11D
4 5
R5 1K
FB7B
60OHM@100MHZ
2 7
C21
0.1UF
C10
10UF
Q24
BSS138
3
1
2
FB5D
4 5
C22
0.1UF
FB9D
4 5
FB9A
1 8
J72
17x2_HDR
2
4
6
8
1
3
7
9
11
13
15
10
12
14
16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
FB5A
1 8
FB7D
4 5
FB6A
60OHM@100MHZ
1 8
FB11B
2 7
C5
22UF
FB7A
1 8
C2
0.1UF
FB10A
1 8
FB10C
60OHM@100MHZ
3 6
RP104A
1K
18
RP104C
1K
36
U3
MAX3243
26
28
24
1
2
27
3
14
13
12
20
18
17
16
15
19
9
10
11
4
5
6
7
8
23
22
21 25
VCC
C1+
C1-
C2+
C2-
V+
V-
T1IN
T2IN
T3IN
R2OUTB
R2OUT
R3OUT
R4OUT
R5OUT
R1OUT
T1OUT
T2OUT
T3OUT
R1IN
R2IN
R3IN
R4IN
R5IN
FORCEON
FORCEOFF#
INVALID# GND
FB5B
2 7
FB11A
1 8
RP102B
1K
27
FB7C
63
FB8B
2 7
RP102A
1K
18
FB6B
2 7
RP102C
1K
36
242
Design Guide