Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel

Pentium

4 Processor-M and Intel

845MP/845MZ Chipset Platform

Design Guide 29

are Intel’s best guidelines based on extensive simulation and experimentation that make assumptions,

which may be different than an OEM's system design. The most accurate way to understand the signal

integrity and timing of the system bus in your platform is by performing a comprehensive simulation

analysis. It is conceivable that adjustments to trace impedance, line length, termination impedance, board

stackup and other parameters can be made that improve system performance.

Refer to the Mobile Intel

Pentium

4 Processor-M Datasheet for a system bus signal list, signal types

and definitions.

3.4. General Topology and Layout Guidelines

The following topology and layout guidelines are preliminary and subject to change. The guidelines are

derived from empirical testing with very preliminary Intel 845MP/845MZ Chipset package models.

3.4.1. Design Recommendations

Below are the design recommendations for the data, address, strobes, and common clock signals. For the

following discussion, the pad is defined as the attach point of the silicon die to the package substrate.

DATA:

Data signals of the same source synchronous group should be routed to the same pad-to-pad length

within ± 0.100 inches of the associated strobes. As a result, additional trace will be added to some data

nets on the system board in order for all trace lengths within the same data group to be the same length (±

0.100 inches) from the pad of the processor to the associated pad of the chipset.

Equation 1. Calculation to Determine Package Delta Addition to Motherboard Length for UP

Systems

)cs_pkglen(cs_pkglen)cpu_pkglenn(cpu_pkgledelta

strobenet*strobenetnet,strobe

−+−=

Refer to the Intel

845MP or 845MZ Chipset Memory Controller Hub Mobile (MCH-M) datasheet for

MCH-M package dimensions and refer to the Intel

Mobile Pentium

4 Processor-M in the 478 Pin

Package/ Signal Integrity Models for package dimensions.

* Strobe package length is the average of the strobe pair.

ADDRESS:

Address signals follow the same rules as data signals except they should be routed to the same pad-to-

pad length within ± 0.200 inches of the associated strobes. Address signals may change layers if the

reference plane remains Vss.

STROBE:

A strobe and its complement should be routed to a length equal to their corresponding data group's mean

pad-to-pad length ± 0.025 inches

COMMON CLOCK:

Common clock signals should be routed to a minimum pin-to-pin motherboard length of 1.5 inches and a

maximum motherboard length of 10.0 inches.