Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

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Mobile Intel

Pentium

4 Processor-M and Intel

845MP/845MZ Chipset Platform

Design Guide 3

Contents

1. Introduction ................................................................................................................................ 14

1.1. Related Documentation................................................................................................. 15

1.2. Conventions and Terminology....................................................................................... 16

1.3. Mobile Intel

Pentium

4 Processor-M in 478- Pin Package......................................... 18

1.4. Intel 845MP/845MZ Chipset .......................................................................................... 19

1.4.1. Intel Memory Controller Hub (MCH-M)........................................................ 20

1.4.1.1. Processor System Bus Support...................................................... 21

1.4.1.2. Integrated System Memory DRAM Controller ................................ 21

1.4.1.2.1. Accelerated Graphics Port (AGP) Interface ................. 21

1.4.1.3. Packaging/Power............................................................................ 22

1.4.1.4. I/O Controller Hub (ICH3-M)........................................................... 22

1.4.1.4.1. Packaging/Power.......................................................... 22

1.4.1.5. Firmware Hub (FWH) ..................................................................... 22

1.4.1.5.1. Packaging/Power.......................................................... 22

1.4.2. Bandwidth Summary ................................................................................... 22

2. General Design Considerations ................................................................................................. 24

2.1. Nominal Board Stackup................................................................................................. 24

3. Processor System Bus Design Guidelines ................................................................................ 25

3.1. Introduction....................................................................................................................25

3.2. Processor System Bus (PSB) Routing Guidelines ........................................................ 26

3.2.1. Return Path Evaluation ............................................................................... 27

3.2.2. GTLREF Layout and Routing Recommendations....................................... 28

3.3. Processor Configuration................................................................................................ 28

3.3.1. Mobile Intel Pentium 4 Processor-M in the 478 -Pin Package

Configuration ............................................................................................... 28

3.4. General Topology and Layout Guidelines ..................................................................... 29

3.4.1. Design Recommendations .......................................................................... 29

3.4.2. Source Synchronous (SS) Signals .............................................................. 30

3.4.3. Common Clock (CC) AGTL+ Signals.......................................................... 32

3.4.3.1. CC Topology with ODT................................................................... 32

3.4.4. Asynchronous AGTL+ Signals .................................................................... 34

3.4.4.1. CPU THRMTRIP# Circuit Recommendation.................................. 35

3.4.4.1.1. Topology #1: Asynchronous AGTL+ Signals Driven by

the Processor; FERR#, IERR#, PROCHOT# and

THRMTRIP#................................................................. 36

3.4.4.1.2. Topology #2, #2A: Asynchronous AGTL+ Signals Driven

by ICH3-M..................................................................... 36

3.4.4.1.3. Topology #2B: Asynchronous AGTL+ Signals Driven by

ICH3-M to Both CPU and FWH; INIT#......................... 37

3.4.4.2. Voltage Translator Circuit ............................................................... 38

3.5. ITP Debug Port.............................................................................................................. 38

3.5.1.1. Logic Analyzer Interface (LAI) ........................................................ 38

3.5.1.1.1. Mechanical Considerations .......................................... 38

3.5.1.1.2. Electrical Considerations .............................................. 39

4. Processor Power Requirements ................................................................................................ 40

4.1. General Description....................................................................................................... 40

4.2. Power Delivery Architectural Block Diagram ................................................................. 41