Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
34 Design Guide
R
3.4.4. PWRGOOD and Asynchronous AGTL+ Signals
Table 8. Asynchronous AGTL+ Nets
Signal
Names
Description Topology
#
CPU
IO
Type
Output Output
Buffer
Type
Output
Power
Well
Input Input Power
Well
FERR# Floating point
error
1 O CPU OD AGTL+ N/A ICH3-M Main I/O
(3.3V)
IERR# Internal error 1 O CPU OD AGTL+ N/A System
Receiver
Vcc_Receiver
PROCHOT# Thermal sensor 1 O CPU OD AGTL+ N/A System
Receiver
Vcc_Receiver
THRMTRIP# Thermal sensor 1 O CPU OD AGTL+ N/A System
Receiver
Vcc_Receiver
LINT1/INTR Local interrupts 2 I ICH3-M CMOS CPU I/O
(VCC_CPU)
CPU N/A
LINT0/NMI Local interrupts 2 I ICH3-M CMOS CPU I/O
(VCC_CPU)
CPU N/A
DPSLP# Deep sleep 2 I ICH3-M CMOS CPU I/O
(VCC_CPU)
CPU N/A
SLP# Sleep 2 I ICH3-M CMOS CPU I/O
(VCC_CPU)
CPU N/A
STPCLK# Processor stop
clock
2 I ICH3-M CMOS CPU I/O
(VCC_CPU)
CPU N/A
IGNNE# Ignore next
numeric error
2 I ICH3-M CMOS CPU I/O
(VCC_CPU)
CPU N/A
SMI# System
management
interrupt
2 I ICH3-M CMOS CPU I/O
(VCC_CPU)
CPU N/A
A20M# Address 20
mask
2 I ICH3-M CMOS CPU I/O
(VCC_CPU)
CPU N/A
INIT# Processor
initialize
2B I ICH3-M CMOS CPU I/O
(VCC_CPU)
CPU,
FWH
N/A, 3.3 V
CPUPREF# GHI# 2 1 ICH3-M OD CMOS N/A CPU N/A
PWRGOOD System power
good
2A I ICH3-M OD CMOS N/A CPU N/A