Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
4 Design Guide
R
4.3. Processor Phase Lock Loop Design Guidelines............................................................41
4.3.1. Filter Specifications for VCCA, VCCIOPLL, and VSSA ...............................41
4.4. Voltage and Current.......................................................................................................44
4.4.1. Voltage Identification....................................................................................44
4.4.2. V
CC
Power Sequencing ................................................................................44
4.4.2.1. Core Converter Soft Start Timer .....................................................44
4.4.2.2. Power On/Off Sequencing ..............................................................44
4.5. Voltage Regulator Design Recommendations ...............................................................45
4.6. Processor Decoupling Recommendation ......................................................................45
4.6.1. Transient Response.....................................................................................46
4.6.2. Processor Voltage Plane .............................................................................46
4.6.3. High Frequency Decoupling.........................................................................47
4.6.4. Bulk Decoupling...........................................................................................47
4.7. Thermal Power Dissipation............................................................................................47
4.8. Voltage Regulator Topology...........................................................................................49
4.9. Voltage Regulator Layout Recommendations ...............................................................49
5. Double Data Rate Synchronous DRAM (DDR-SDRAM) System Memory Design Guidelines...54
5.1. Introduction ....................................................................................................................54
5.2. DDR System Memory Topology and Layout Design Guidelines....................................55
5.2.1. Data Signals – SDQ[63:0], SDQS[8:0], SCB[7:0] ........................................55
5.2.1.1. Data to Strobe Length Matching Requirements..............................57
5.2.1.2. Strobe to Clock Length Matching Requirements ............................59
5.2.1.3. Data Routing Example ....................................................................61
5.2.2. Control Signals – SCKE[3:0], SCS#[3:0] .....................................................61
5.2.2.1. Control Group Signal Length Matching Requirements....................64
5.2.2.2. Control Routing Example ................................................................65
5.2.3. Command Signals – SMA[12:0], SBS[1:0], SRAS#, SCAS#, SWE# ..........66
5.2.3.1. Command Topology 1 Solution.......................................................67
5.2.3.1.1. Routing description for Command Topology 1..............67
5.2.3.1.2. Command Group Signal Length Matching
Requirements................................................................69
5.2.3.2. Command Topology 2 Solution.......................................................72
5.2.3.2.1. Routing Description for Command Topology 2 .............72
5.2.3.2.2. Command Group Signal Length Matching
Requirements................................................................74
5.2.3.2.3. Command Routing Example for Topology 2 Solution...76
5.2.4. Clock Signals – SCK[5:0], SCK#[5:0] ..........................................................77
5.2.4.1. Clock Group Signal Length Matching Requirements ......................79
5.2.5. Feedback - RCVENOUT#, RCVENIN# .......................................................81
6. AGP Port Design Guidelines ......................................................................................................85
6.1. AGP Interface ................................................................................................................85
6.2. AGP 2.0 .........................................................................................................................86
6.2.1. AGP Interface Signal Groups ......................................................................86
6.3. AGP Routing Guidelines ................................................................................................87
6.3.1. 1X Timing Domain Routing Guidelines........................................................87
6.3.1.1. Trace Length Requirements for the AGP 1X ..................................87
6.3.1.2. Trace Spacing Requirements .........................................................88
6.3.1.3. Trace Length Mismatch ..................................................................88
6.3.2. 2X/4X Timing Domain Routing Guidelines ..................................................88
6.3.2.1. Trace Length Requirements for AGP 2X/4X...................................88
6.3.2.2. Trace Spacing Requirements .........................................................89