Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide
Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
Design Guide 5
R
6.3.2.3. Trace Length Mismatch Requirements .......................................... 90
6.3.3. AGP Clock Skew......................................................................................... 91
6.3.4. AGP Signal Noise Decoupling Guidelines................................................... 91
6.3.5. AGP Routing Ground Reference................................................................. 92
6.3.6. Pull-ups ....................................................................................................... 92
6.3.7. AGP VDDQ and Vref................................................................................... 93
6.3.8. Vref Generation for AGP 2.0(2X & 4X) ....................................................... 93
6.3.8.1. 3.3-V AGP Interface (AGP 2x)........................................................ 93
6.3.8.2. 1.5-V AGP interface (AGP 2x & 4x)................................................ 93
6.3.9. Compensation ............................................................................................. 94
7. MCH-M PLL Requirements........................................................................................................ 95
7.1. MCH-M PLL Power Delivery.......................................................................................... 95
8. Hub Interface.............................................................................................................................. 97
8.1. Hub Interface Routing Guidelines ................................................................................. 97
8.2. Hub Interface Data Signals ........................................................................................... 97
8.3. Hub Interface Strobe Signals ........................................................................................ 98
8.4. HUBREF Generation/Distribution .................................................................................. 98
8.5. Hub Interface Decoupling Guidelines............................................................................ 99
9. I/O Subsystem.......................................................................................................................... 100
9.1. IDE Interface ............................................................................................................... 100
9.1.1. Primary IDE Connector Requirements...................................................... 102
9.1.2. Secondary IDE Connector Requirements ................................................. 103
9.2. PCI............................................................................................................................... 104
9.3. AC’97........................................................................................................................... 104
9.3.1. Four-Layer Layout Example ...................................................................... 105
9.3.2. AC’97 Audio Codec Detect Circuit and Configuration Options.................. 106
9.3.3. Valid Codec Configurations....................................................................... 106
9.3.4. SPKR Pin Consideration ........................................................................... 106
9.3.5. AC’97 Routing ........................................................................................... 107
9.3.6. Motherboard Implementation .................................................................... 108
9.4. USB Guidelines and Recommendations ..................................................................... 108
9.4.1. General Routing and Placement ............................................................... 108
9.4.2. USB Trace Separation .............................................................................. 109
9.4.3. USB Trace Length Matching ..................................................................... 109
9.4.4. Plane Splits, Voids and Cut-Outs (Anti-Etch) ............................................ 110
9.4.4.1. VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)...................... 110
9.4.4.2. GND Plane Splits, Voids, and Cut-Outs (Anti-Etch) ..................... 110
9.4.4.3. EMI Recommendation .................................................................. 110
9.5. IOAPIC (I/O Advanced Programmable Interrupt Controller) ....................................... 110
9.5.1. IOAPIC Disabling Options ......................................................................... 110
9.5.1.1. Recommended Implementation ................................................... 110
9.5.2. PIRQ Routing Example ............................................................................. 111
9.6. SMBus 2.0/SMLink Interface....................................................................................... 112
9.6.1. SMBus Architecture and Design Considerations ...................................... 113
9.6.1.1. SMBus Design Considerations ..................................................... 113
9.6.1.2. General Design Issues/Notes....................................................... 113
9.6.1.3. The Unified Vcc_ Suspend Architecture....................................... 113
9.6.1.4. The Unified Vcc_Core Architecture .............................................. 114
9.6.1.5. Mixed Architecture........................................................................ 114
9.7. FWH ............................................................................................................................ 115