Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
Design Guide 57
R
5.2.1.1. Data to Strobe Length Matching Requirements
The data signals SDQ[63:0] and the check bit signals [7:0] are grouped by byte lane and associated with
a data strobe, SDQS[7:0]. The data signals and check bit signals must be length matched to their
associated strobe within
± 25mils. For SO-DIMM0 this length matching includes the MCH-M package
length and the motherboard trace length to the pads of the SO-DIMM0 connector (MCH-M package +
L1 + L2). For SO-DIMM1 this length matching includes the MCH-M package length and the
motherboard trace length to the pads of the SO-DIMM1 connector (MCH-M package + L1 + L2 + L3).
• Associated SDQS Length = X
• SDQ/SCB Byte Group Length = Y, where ( X – 25 mils ) ≤ Y ≤ ( X + 25 mils )
• Length X and Y include the compensated MCH-M Package Length + the Motherboard Trace
Length
No length matching is required from the second SO-DIMM to the parallel termination resistors. The
table and diagram below depict the length matching requirements between the DQ, CB, and DQS signals.
Table 15. DQ/CB to DQS Length Mismatch Mapping
Signal Length Mismatch Relative To
SDQ[7:0] ±25 mils SDQS0
SDQ[15:8] ±25 mils SDQS1
SDQ[23:16] ±25 mils SDQS2
SDQ[31:24] ±25 mils SDQS3
SDQ[39:32] ±25 mils SDQS4
SDQ[47:40] ±25 mils SDQS5
SDQ[55:48] ±25 mils SDQS6
SDQ[63:56] ±25 mils SDQS7
SCB[7:0] ±25 mils SDQS8