Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
Design Guide 61
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5.2.1.3. Data Routing Example
Figure 23 is an example of a board routing for the data signal group. Data routing is shown in red. The
majority of the Data signal route is on an internal layer, both external layers can used for parallel
termination R-pack placement.
Figure 23. Data Signal Group Routing Example
5.2.2. Control Signals – SCKE[3:0], SCS#[3:0]
The MCH-M control signals, SCKE[3:0] and SCS#[3:0], are common clocked signals. They are
“clocked” into the DDR SDRAMs using clock signals SCK/SCK#[5:0]. The MCH-M drives the control
and clock signals together, with the clocks crossing in the valid control window. The MCH-M provides
one chip select and one clock enable signal per SO-DIMM physical device row. Two chip-selects and
two clock-enables will be routed to each SO-DIMM. Table 16 summarizes the control signal mapping.
MCH
Data signals