Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
Design Guide 63
R
Table 17. Control Signal Group Routing Guidelines1
Parameter Routing Guidelines Figure
Signal Group Control – SCS#[3:0], SCKE[3:0]
Topology Point to Point Parallel Termination Figure 24,
Figure 27
Reference Plane Ground Referenced
2
Characteristic Trace Impedance (Zo) 55 Ω ± 15%
Trace Width Inner Layer= 4 mils
Outer Layer= 5 mils
Trace to space ratio 1:2 (e.g. 4mil trace 8mil space)
Group Spacing Isolation spacing from non-DDR related signals =
20 mils
Trace Length L1 – MCH-M Control Signal Ball
to SO-DIMM Pad
Min = 0.5”
Max= 5.0”
Figure 24
Trace Length L2 – SO-DIMM Pad to Rtt Pad Max = 2.0” Figure 24
Parallel Termination Resistor (Rtt) 56 Ω +/- 5% (see note below) Figure 24
Maximum Recommended motherboard via
Count per signal
3 vias
3
Figure 27
Length Matching Requirements SCS#/SCKE[3:0] to SCK/SCK#[5:0]
See section 0 for details
Figure 26
NOTES:
1. Recommendations may change in a later revision of the design guide based on a post silicon simulation
analysis.
2. Where ever possible control signal should be routed on adjacent layers to the referenced plane. See Figure 25
below for example, the control signal routing should only route on Signal 1 and Signal 2 layer where Signal 1
may be external (microstrip) and Signal 2 may be internal (stripline) or where Signal 1 is internal (stripline) and
Signal 2 is external (microstrip).
3. It is possible to route control using 2 vias if one via is shared that connect to SO-DIMM and parallel termination
resistor.
Note: The overall maximum and minimum lengths to the SO-DIMM must comply with clock length matching
requirements.
Figure 25. Referencing Plane Stack-up