Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
Design Guide 67
R
5.2.3.1. Command Topology 1 Solution
5.2.3.1.1. Routing description for Command Topology 1
Refer to Figure 28 and Figure 31 for clarification of the description below. The command signal routing
should transition from an external layer to an internal signal layer under the MCH-M. Keep to the same
internal layer until transitioning back to an external layer immediately prior to connecting the appropriate
pad of the SO-DIMM0 connector. At the SO-DIMM0 layer transition continue the signal route on the
same internal layer to the series resistor Rd2d, collocated to SO-DIMM1. At this resistor the signal
should transition to an external layer immediately prior to the pad of Rd2d. After the series resistor,
Rd2d, continue the signal route on the external layer landing on the appropriate connector pad
of SO-
DIMM1. After SO-DIMM1, transition to the same internal layer or stay on the external layer and route
the signal to Rt.
External trace lengths should be minimized. It is suggested that the parallel termination(Rt) be placed on
both sides of the board to simplify routing and minimize trace lengths. All internal and external signals
should be ground referenced to keep the path of the return current continuous. It is suggested that
command be routed on same internal layer.
Resistor packs are acceptable for the series (Rd2d) and parallel (Rt) command termination resistors but
command signals can’t be placed within the same Rpacks as data, strobe or control signals. The diagrams
and tables below depict the recommended topology and layout routing guidelines for the DDR-SDRAM
command signals routing to SO-DIMM0 and SO-DIMM1 for topology 1.Collocating the series resistor,
Rd2d, and SO-DIMM1 allows for the elimination of one via from the signal route.
Figure 28. Command Signal Routing Topology 1
w
Rd2d
SO-DIMM1 PAD SO-DIMM0 PAD
Vtt
MCH-M
Pad
MCH-M Package
L1
L3
w
L2
Rt
L4