Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
Design Guide 7
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10. Platform Clock Routing Guidelines .......................................................................................... 142
10.1. Clock Generation......................................................................................................... 142
10.2. Clock Control............................................................................................................... 145
10.2.1. CK-408 Delay Circuit Recommendation.................................................... 145
10.2.2. SLP_S1# ................................................................................................... 145
10.2.3. SLP_S3# ................................................................................................... 145
10.3. Clock Group Topology and Layout Routing Guidelines............................................... 146
10.3.1. HOST_CLK Clock Group .......................................................................... 146
10.3.1.1. End Of Line Termination Topology............................................... 146
10.3.1.2. Source Shunt Termination Topology............................................ 148
10.3.2. CLK66 Clock Group .................................................................................. 151
10.3.3. AGPCLK Clock Group............................................................................... 152
10.3.4. CLK33 Clock Group .................................................................................. 154
10.3.5. CLK14 Clock Group .................................................................................. 154
10.3.6. PCICLK Clock Group ................................................................................ 156
10.3.7. USBCLK Clock Group............................................................................... 158
11. Platform Power Guidelines....................................................................................................... 159
11.1. Definitions.................................................................................................................... 159
11.2. Platform Power Requirements .................................................................................... 160
11.2.1. Platform Power Delivery Architectural Block Diagram .............................. 160
11.3. Voltage Supply............................................................................................................. 161
11.3.1. Power Management States ....................................................................... 161
11.3.2. Power Supply Rail Descriptions ................................................................ 161
11.3.3. Power Supply Control Signals ................................................................... 162
11.3.3.1. SLP_S3# .................................................................................... 162
11.3.3.2. SLP_S5# .................................................................................... 162
11.4. Platform Power Sequencing Requirements ................................................................ 162
11.4.1. Processor Power Sequencing................................................................... 162
11.4.1.1. Core Converter Soft Start Timer................................................... 162
11.4.2. ICH3-M Power Sequencing....................................................................... 162
11.4.2.1. 1.8 V/3.3 V Sequencing ................................................................ 162
11.4.2.2. 3.3-V/V5REF and 3.3SUS/V5REF_SUS Sequencing .................. 163
11.4.3. MCH-M Power Sequencing Requirements ............................................... 165
11.4.4. DDR Power Sequencing Requirements .................................................... 165
11.5. Decoupling Recommendations ................................................................................... 166
11.5.1. Transient Response .................................................................................. 166
11.5.2. Processor Decoupling Recommendations ................................................ 166
11.5.3. ICH3-M Decoupling Recommendations.................................................... 166
11.5.3.1. 1.8-V Power Supply Rails ............................................................. 166
11.5.3.2. 3.3-V Power Supply Rails ............................................................. 167
11.5.4. MCH-M Decoupling Recommendations.................................................... 167
11.5.4.1. VCC_CORE, VTT Processor System Bus, VTT .......................... 167
11.5.4.2. 1.5-V AGP/CORE ......................................................................... 167
11.5.4.3. 1.8-V Hub Interface ...................................................................... 167
11.5.5. 2.5-V MCH-M System Memory High Frequency Decoupling .................... 167
11.5.6. 2.5-V MCH-M System Memory Low Frequency Bulk Decoupling............. 168
11.5.7. 2.5-V SO-DIMM System Memory High Frequency Decoupling ................ 168
11.5.8. 2.5-V SO-DIMM System Memory Low Frequency Decoupling ................. 168
11.5.9. 1.25-V DDR VTT High Frequency Decoupling Requirements .................. 168
11.5.10. 1.25-V DDR VTT Low Frequency Bulk Decoupling Requirements ........... 169
11.5.11. 1.5-V AGP Decoupling .............................................................................. 169
11.5.12. 1.8-V Hub Interface Decoupling ................................................................ 169