Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
Design Guide 73
R
Table 19. Command Signal Group Routing Guidelines
Parameter Routing Guidelines Figure
Signal Group Command – SMA[12:0], SBS[1:0], SRAS#,
SCAS#, SWE#
Topology T Topology Figure 32,
Figure 35
Reference Plane Ground Referenced
2
Characteristic Trace Impedance (Zo) 55 Ω ± 15%
Trace Width Inner layers= 4 mils
Outer layer= 5 mils
Trace to space ratio 1:2 (e.g. 4mil trace 8mil space)
Group Spacing Isolation spacing from non-DDR related signals =
20 mils
Trace Length L1 – MCH-M Command Signal
ball to Rs Pad
Min = 0.5”
Max= 5.0”
Figure 32
Trace Length L2 – Rd2d Pad to SO-DIMM0
Pad
Max = 1.0” Figure 32
Trace Length L3 – Rd2d Pad to SO-DIMM1 Min = 0.4”
Max=1.75”
Figure 32
Trace Length L4 – SO-DIMM1 Pad to Rt Pad Max = 0.25” Figure 32
Series Dampening Resistor (Rd2d) 10 Ω (see note below)
1
Figure 32
Parallel Termination Resistor (Rt) 56 Ω ± 5%
1
Figure 32
Maximum Recommended motherboard via
Count per signal
6 vias
3
Figure 35
Length Matching Requirements CMD to SCK/SCK#[5:0]
See 5.2.3.2.2 for details
Figure 34
NOTES:
1. Recommendation may change in a later revision of the design guide based on a post silicon simulation
analysis.
2. Wherever possible command signals should be routed on adjacent layers to the referenced plane. See Figure
33 for example. The command signal routing should only route on Signal 1 and Signal 2 layer where Signal 1
may be external (microstrip) and Signal 2 may be internal (stripline) or where Signal 1 is internal (stripline) and
Signal 2 is external (microstrip).
3. It is possible to route using 3 vias if one via is shared that connect to SO-DIMM0 and Rd2d resistor.
Note: The overall maximum and minimum lengths to the SO-DIMM must comply with clock length matching
requirements.
Figure 33. Referencing Plane Stack-up