Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel

Pentium

4 Processor-M and Intel

845MP/845MZ Chipset Platform

Design Guide 85

6. AGP Port Design Guidelines

For detailed AGP interface functionality (e.g., protocols, rules, signaling mechanisms), refer to the latest

AGP Interface Specification, Revision 2.0, which can be obtained from http://www.agpforum.org. This

design guide (

Intel

845MP/845MZ Chipset Platform Design Guide) focuses only on specific Intel

845MP/845MZ chipset platform recommendations.

6.1. AGP Interface

The AGP Interface Specification Revision 2.0 enhances the functionality of the original AGP Interface

Specification (revision 1.0) by allowing 4X data transfers (4 data samples per clock) and 1.5-volt

operation. In addition to these major enhancements, additional performance enhancement and

clarifications, such as

fast write capability, are included in Revision 2.0 of the AGP Interface

Specification

The 4X operation of the AGP interface provides for “quad-sampling” of the AGP AD (Address/Data)

and SBA (Side-band Addressing) buses. That is, the data is sampled four times during each 66-MHz

AGP clock. This means that each data cycle is ¼ of a 15 ns (66-MHz clock) or 3.75 ns. It is important to

realize that 3.75 ns is the data cycle time; not the clock cycle time. During 2X operation, the data is

sampled twice during a 66-MHz clock cycle, therefore, the data cycle time is 7.5 ns.

In order to allow for these high-speed data transfers, the 2X mode of AGP operation uses source

synchronous data strobing. During 4X operation, the AGP interface uses differential source synchronous

strobing.

With data cycle times as small as 3.75 ns, and setup/hold times of 1 ns, propagation delay mismatch is

critical. In addition to reducing propagation delay mismatch, it is important to minimize noise. Noise on

the data lines will cause the settling time to be large. If the mismatch between a data line and the

associated strobe is too great, or there is noise on the interface, incorrect data will be sampled.

The low-voltage operation on AGP (1.5 V) requires even more noise immunity. For example, during 1.5-

V operation, V

max

is 570 mV. Without proper isolation, crosstalk could create signal integrity issues.

A single AGP connector is supported by the Intel 845MP/845MZ chipset MCH-M AGP interface.

LOCK# and SERR#/PERR# are not supported. The AGP buffers operate in only one mode.

1.5-V drive, not 3.3-V safe. This mode is compliant with the AGP 2.0 spec. The Intel 845MP/845MZ

chipset can make use of a 1.5V only AGP connector.

AGP 4X, 2X and 1X must operate at 1.5 V. The AGP interface supports up to 4X AGP signaling. AGP

semantic cycles to DRAM are not snooped on the host bus.

The Intel 845MP/845MZ chipset MCH-M supports PIPE# or SBA[7:0] AGP address mechanisms, but

not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be selected during system

initialization

The AGP interface is clocked from the 66-MHz clock (pin 3V66). The AGP interface is synchronous to

the host and system memory interfaces with a clock ratio of 1:2 (66 MHz: 133 MHz) and to the hub

interface with a clock ratio of 1:1 (66 MHz : 66 MHz).