Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
90 Design Guide
R
Table 27. Layout Routing Guidelines for AGP 2X/4X Signals
Signal
Maximum
Length
(inch)
Trace Space
(mils)
(4 mil traces)
Length
Mismatch
(inch)
Relative To Notes
2X/4X
Timing
Domain
Set#1
6 8 ± 0.1 AGP_ADSTB0
and
AGP_ADSTB0#
AGP_ADSTB0,
AGP_ADSTB0# must be the
same length (±10 mils)
2X/4X
Timing
Domain
Set#2
6 8 ± 0.1 AGP_ADSTB1
and
AGP_ADSTB1#
AGP_ADSTB1,
AGP_ADSTB1# must be the
same length ±10 mils)
2X/4X
Timing
Domain
Set#3
6 8 ± 0.1 AGP_SBSTB
and
AGP_SBSTB #
AGP_SBSTB, AGP_SBSTB#
must be the same length (±10
mils)
6.3.2.3. Trace Length Mismatch Requirements
The length-matching requirement depends on the maximum AGP trace length. If there are no AGP
2X/4X traces longer than 6.0 inches, then signals must be matched within
± 0.1 inches.
Table 28. AGP 2.0 Data Lengths Relative to Strobe Length
Max Trace Length Trace
Spacing
Strobe
Length
Minimum Trace Length Maximum Trace
Length
< 6 in 1:2 X X – 0.1 in X + 0.1 in
The trace length minimum and maximum (relative to strobe length) should be applied to each set of
2X/4X timing domain signals
independently. That is, if AD_STB0 and ADSTB0# are 5 inches, then
AD[15:0] and C/BE[1:0] must be between 4.9 inches and 5.1 inches. However AD_STB1 and
ADSTB1# can be 3.5 inches (and therefore AD[31:16] and C/BE#[3:2] must be between 3.4 inches and
3.6 inches). In addition, all 2X/4X timing domain signals must meet the maximum trace length
requirements.
All signals should be routed as striplines (inner layers).
All signals in a signal group should be routed on the same layer. Routing studies have shown that these
guidelines can be met. The trace length and trace spacing requirements
must not be violated by any
signal. Trace length mismatch for all signals within a signal group should be as close to 0 inches as
possible to provide optimal timing margin. Table 29 shows AGP 2.0 routing summary.