Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
Design Guide 91
R
Table 29. AGP 2.0 Routing Guideline Summary
Signal
Maximum
Length
Trace Spacing
(4 mil traces)
Length Mismatch Relative To Notes
1X Timing
Domain
10 in 4 mils No Requirement N/A None
2X/4X Timing
Domain Set#1
6 in 8 mils ± 0.1 in AD_STB0 and
AD_STB0#
AD_STB0, AD_STB0#
must be the same
length
2X/4X Timing
Domain Set#2
6 in 8 mils ± 0.1 in AD_STB1 and
AD_STB1#
AD_STB1, AD_STB1#
must be the same
length
2X/4X Timing
Domain Set#3
6 in 8 mils ± 0.1 in SB_STB and
SB_STB#
SB_STB, SB_STB#
must be the same
length
Miscellaneous 10 in 8 mils No Requirement N/A PCI_PME#,
AGP_PERR#,
AGP_SERR#
NOTE: Each strobe pair must be separated from other signals by at least 15 mils.
6.3.3. AGP Clock Skew
The maximum total AGP clock skew, between the Intel 845MP/845MZ and the graphics component, is 1
ns for all data transfer modes. This 1 ns includes skew and jitter, which originates on the motherboard,
add-in module (if used), and clock synthesizer. Clock skew must be evaluated not only at a single
threshold voltage, but also at all points on the clock edge that falls in the switching range. The 1-ns skew
budget is divided such that the motherboard is allotted 0.9 ns of clock skew (the motherboard designer
shall determine how the 0.9 ns is allocated between the board and the synthesizer).
6.3.4. AGP Signal Noise Decoupling Guidelines
The following routing guidelines are recommended for the optimal system design. The main focus of
these guidelines is to minimize signal integrity problems on the AGP interface of the Intel
845MP/845MZ chipset (MCH-M). The following guidelines are not intended to replace thorough system
validation on Intel 845MP/845MZ chipset-based products.
• A minimum of six 0.01-µF capacitors are required and must be as close as possible to the MCH-M.
These should be placed within 70 mils of the outer row of balls on the MCH-M for VDDQ
decoupling. The closer the placement, the better the performance.
• The designer should evenly distribute placement of decoupling capacitors in the AGP interface
signal field.
• Intel recommends that the designer use a low-ESL ceramic capacitor, such as with a 0603 body-type
X7R dielectric.
• In order to add the decoupling capacitors within 70 mils of the MCH-M and/or close to the vias, the
trace spacing may be reduced as the traces go around each capacitor. The narrowing of space
between traces should be minimal and for as short a distance as possible (1-inch max.).
• In addition to the minimum decoupling capacitors, the designer should place bypass capacitors at
vias that transition the AGP signal from one reference signal plane to another. On a typical four