Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide
Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
92 Design Guide
R
layer PCB design, the signals transition from one side of the board to the other. One extra 0.01-µF
capacitor is required per 10 vias. The capacitor should be placed as close as possible to the center of
the via field.
6.3.5. AGP Routing Ground Reference
Intel strongly recommends that at least the following critical signals be referenced to ground from the
MCH-M to an AGP connector controller ), using a minimum number of vias on each net: AD_STB0,
AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#, G_TRDY#, G_IRDY#, G_GNT#, and
ST[2:0].
In addition to the minimum signal set listed previously, Intel strongly recommends that half of all AGP
signals be referenced to ground, depending on the board layout. In an ideal design, the complete AGP
interface signal field would be referenced to ground. This recommendation is not specific to any
particular PCB stack-up, but should be applied to all Intel 845MP/845MZ chipset designs.
6.3.6. Pull-ups
AGP control signals require pull-up resistors to VDDQ on the motherboard to ensure they contain stable
values when no agent is actively driving the bus. Intel 845MP/845MZ MCH-M has integrated the
following pull-up resistors, however, the following signals may still require pull-up resistors:
• 1X Timing Domain Signals:
FRAME#
TRDY#
IRDY#
DEVSEL#
STOP#
SERR#
PERR#
RBF#
PIPE#
REQ#
WBF#
GNT#
ST[2:0]
PAR
It is critical that these signals be pulled up to 1.5 V.
The trace stub to the pull-up resistor on 1X timing domain signals should be kept at less than 0.5 inches,
to avoid signal reflections from the stub.
The strobe signals require pull-ups/pull-downs on the motherboard to ensure that they contain
stable values when no agent is driving the bus.
INTA# and INTB# should be pulled to 3.3 V, not VDDQ.
The 2X/4X Timing Domain Signals are:
• AD_STB[1:0] (pull up to 1.5 V)
• SB_STB (pull up to1.5 V)