Manualshelf

Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

ManualsBrandsIntel ManualsOtherIntel Pentium 4 Processor supporting HT Technology 3.00E GHz, 1M Cache, 800 MHz FSB
919293949596979899100
Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
Design Guide 93
R
• AD_STB[1:0]# (pull down to ground)
• SB_STB# (pull down to ground)
The trace stub to the pull-up/pull-down resistor on 2X/4X timing domain signals should be kept to less
than 0.1 inch, to avoid signal reflections from the stub.
The pull-up/pull-down resistor value requirements are shown in Table 30.
Table 30. AGP 2.0 Pull-up Resistor Values
Rmin Rmax
4 KΩ 16 KΩ
The recommended AGP pull-up/pull-down resistor value is 8.2 KΩ.
The MCH-M ST[0] signal needs a site for an external pull-down resistor to ground.
6.3.7. AGP VDDQ and Vref
AGP specifies two separate power planes: VCC and VDDQ. VCC is the core power for the graphics
controller. AGP specifies VCC voltage plane as ALWAYS 3.3 V. VDDQ is the interface voltage. The
external graphics controller may ONLY power the MCH-M AGP I/O buffers with the 1.5-V VDDQ
power pins.
In AGP 1.0 implementations, VDDQ was also 3.3 V. For the designer developing an AGP 1.0
motherboard, there is no distinction between VCC and VDDQ as both are tied to the 3.3-V power plane
on the motherboard. AGP 2.0 requires that these power planes are separate. In conjunction with the 4X
data rate, the AGP 2.0 Interface Specification provides for low-voltage (1.5 V) operation. The VCC and
VDDQ power supplies are such that the VDDQ voltage level is never more than 0.5 V above the VCC
voltage level.
6.3.8. Vref Generation for AGP 2.0(2X & 4X)
6.3.8.1. 3.3-V AGP Interface (AGP 2x)
The 3.3-V AGP interfaces will use only one Vref. That is, only one resistor divider on the AGP
controller that will divide VDDQ down to Vref for MCH-M and AGP controller. For Intel
845MP/845MZ platforms, only 1.5-V interface will be supported.
6.3.8.2. 1.5-V AGP interface (AGP 2x & 4x)
In order to account for potential differences between VDDQ and GND at the MCH-M and graphics
controller, both devices use
source generated Vref. That is, the Vref signal is generated at the graphics
controller and
sent to the MCH-M, and another Vref is generated at the MCH-M and sent to the graphics
controller.
Both the graphics controller and the MCH-M are required to generate Vref. The voltage divider networks
consist of AC and DC elements.