Voltage Regulator-Down (VRD) 10.0

Processor Voltage Requirements

VRD Design Guide 11

2 Processor Voltage Requirements

2.1 Voltage and Current (REQUIRED)

A six-bit VID code transmitted by the processor to the VRD determines a reference output voltage

as described in Table 18. The loadlines in Section 2.2 define the relationship between Vcc and Icc

for the processor at the socket-motherboard interface across pins AC14 and AC15.

Intel performs exhaustive testing against multiple software test vectors and applications to identify

valid processor Vcc operating ranges. Failure to satisfy the loadline, loadline tolerance band, and

overshoot specifications (Sections 2.2, 2.3 and 2.9) may invalidate Intel warranties and lead to

premature processor failure, intermittent system lock-up, and/or data corruption.

2.2 Loadline Definitions (REQUIRED)

To ensure processor reliability and performance, platform DC voltage regulation and transient-

droop noise levels must always be contained within the Vccmin and Vccmax loadline boundaries,

known at the loadline window. Loadline compliance must be guaranteed across 3-sigma

component manufacturing tolerances, thermal variation, and age degradation. Socket loadline

boundaries are defined by the following equations in conjunction with the Vcc regulator design

parameter values defined in Table 4. Loadline voltage tolerance is defined in Section 2.3. In these

equations, VID, R

, and TOB are known. Plotting Vcc in these equations while varying Icc from

0 A to Iccmax establishes the Vccmax and Vccmin loadlines. Vccmax establishes the maximum

DC loadline boundary and Vccmin establishes the minimum AC and DC voltage boundary. Short

transient bursts above the Vccmax loadline are permitted; this condition is defined in Section 2.9.

Table 3. Socket Loadline Equations

Loadline Equation

Vccmax Vcc = VID – (R

* Icc)

Vcctyp Vcc = VID – TOB - (R

* Icc)

Vccmin Vcc = VID – 2*TOB - (R

* Icc)

NOTE: RLL is the socket loadline impedance (slope)

Socket loadline recommendations are established to provide guidance for satisfying processor die

loadline specifications, which are defined in the processor datasheet Die loadline requirements

must be satisfied at all times and may require adjustment in the socket loadline value.