Voltage Regulator-Down (VRD) 10.0

Processor Voltage Requirements
R
12 VRD Design Guide
Table 4. Vcc Regulator Design Parameters
VR Configuration Iccmax
VR
TDC
Dynamic
Icc
R
LL
TOB
Maximum
VID
478_VR_CONFIG_A 91 A 80 A 70 A
1.24 mΩ
±19 mV 1.4 V
478_VR_CONFIG_B 78 A 68 A 55 A
1.3 mΩ
±25 mV 1.4 V
478_VR_CONFIG_C 70 A 63 A 50 A
1.5 mΩ
±25 mV 1.6 V
478_VR_CONFIG_D 91 A 80 A 70 A
1.5 mΩ
±19 mV 1.6 V
VRD transient loadline circuits should meet or exceed rated conditions defined in Table 4. For
example, 478_VR_CONFIG_A requires a loadline slope of 1.24 mΩ. A transient loadline slope of
1.0 mΩ will satisfy this requirement without adversely impacting system performance or processor
reliability. However, the static loadline condition must be set to the recommended value.
Operating at a low loadline resistance will result in higher processor operating temperature, which
may result in damage or a reduced processor life span. Processor temperature rise from higher
functional voltages may lead to operation at low power states which directly reduces processor
performance. Operating at a higher loadline resistance will result in minimum voltage violations
which may result in system lock-up, blue screening, or data corruption.
Table 4 provides a comprehensive list of socket 478 voltage regulator design configurations. The
specific configuration to be adopted by VRD hardware will depend on the specific processors the
design is intended to support. It is common for a motherboard to support processors that require
different VR configurations. In this case, the Vcc regulator design must meet the specifications of
all processors supported by that board. For example, If a motherboard is targeted to support
processors that require 478_VR_CONFIG_A and 478_VR_CONFIG_C, then the voltage
regulator must have the ability to support 80 A of VR TDC, 91 A of electrical peak current, satisfy
overshoot requirements of Section 2.9 with a dynamic load step of 70 A, satisfy a VRD tolerance
band of ±19 mV (see Section 2.3), and have the ability to detect the specific processor installed in
the socket and automatically configure the loadline slope (RLL) to the correct value. VR
configuration requirements will be defined in processor data sheets. However, Intel is aware that
some data sheets do not contain this necessary information and a partial mapping of processors to
VR configurations is provided in Table 5.