Voltage Regulator-Down (VRD) 10.0

Processor Voltage Requirements

18 VRD Design Guide

To properly calibrate the socket loadline parameter, the VR designer must excite the processor

socket with a current step that generates a voltage droop which must be checked against the

loadline window requirements. The table below identifies the steady state and transient current

values to use for this calibration. For additional information, please consult the Loadline

Calculator for the appropriate Intel processor.

Table 10. Intel

Processor Current Step Values for Transient Loadline Testing

VR Configuration Starting Current Ending Current Dynamic Current Step

478_VR_CONFIG_A 21 A 91 A 70 A

478_VR_CONFIG_B 23 A 78 A 55 A

478_VR_CONFIG_C 20 A 70 A 50 A

478_VR_CONFIG_D 21 A 91 A 70 A

VRD designs must be loadline compliant across the full tolerance band window to avoid data

corruption, system lock-up, and reduced performance. When validating a system’s loadline, a

single measurement is statistically insignificant and cannot represent the response variation seen

across the entire high volume manufacturing population of VRD designs. A typical loadline may

fit in the specification window, however designs residing elsewhere in the tolerance band

distribution may violate the specifications. For example, Figure 5 Example A shows a loadline that

is contained in the specification window and, in this single instance, complies with Vccmin and

Vccmax specifications. The positioning of this loadline will shift up and down as the tolerance

drifts from typical to the design limits. Figure 5 Example B shows that Vccmax limits will be

violated as the component tolerances shift the loadline to the upper tolerance band limits. Figure 5

Example C shows that the Vccmin limits will be violated as the component tolerances shift the

loadline to the lower tolerance band limits.

To satisfy specifications across high volume manufacturing variation, a typical loadline must be

centered in the loadline window and have a slope equal to the value specified in Table 4. Figure 6

Example A shows a loadline that meets this condition. Under full 3-sigma tolerance band

variation, the loadline slope will intercept the Vccmax loadline (Figure 6 Example B) or Vccmin

loadline (Figure 6 Example C) limits.