Voltage Regulator-Down (VRD) 10.0

Processor Voltage Requirements
R
VRD Design Guide
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2.3.2.3 FET RDS-ON Current Sense TOB Calculations
Current can be determined by sensing the voltage across the VRD switching FET’s drain to source
‘on’ resistance. While this provides a direct method of voltage to current conversion, the standard
FET RDS-ON tolerance of ~20% is not acceptable to satisfy tolerance band requirements. If RDS-
ON sensing is to be applied, FET thermal compensation is required (see Section 2.4) together with
a tight FET RDS-ON distribution (approximately 5% at 3-sigma). Since boards are generally built
with FETs from similar manufacturing lots, process to process variation is not random and the
RDS-ON parameter may not be reduced through statistical analysis.
2.4 VRD Thermal Compensation (REQUIRED)
Intel processors in Socket 478 can draw significant levels of current, resulting in a varying
temperature gradient across electrical components. Electrical parameters of these components are
functions of temperature and their values will drift with the thermal gradient. This drift will result
in a loadline violation if not minimized. To ensure compliance to specifications, the voltage
regulator requires thermal compensation.
Thermal compensation allows the processor Vcc voltage regulator to respond to temperature drift
in VRD electrical parameters. It is required to ensure that regulators using inductor or FET RDS-
ON current sensing maintain a stable voltage over the full range of load current and system
temperatures.
If thermal compensation is not included, the output voltage of the regulator will droop as the
resistance of the sense element increases with temperature. With the increased resistance, the
regulator falsely detects an increase in load current and regulates to a lower voltage. Thermal
compensation prevents this thermally induced voltage droop by adjusting the feedback path based
on the temperature of the regulator. This is accomplished by placing a thermistor in the feedback
network (tuned with a proper resistor configuration) to negate the effects of the increased
resistance of the sense element.
The thermal compensation circuit is to be validated by running the regulator at VR TDC for 30 to
45 minutes. This is to ensure the board is thermally saturated and system temperatures have
reached a maximum steady state condition. If the thermal compensation has been properly
implemented, the output voltage will only drift 1-2 mV from its coolest temperature condition. If
the thermal compensation has not been properly implemented, voltage error can be measured in
the 10’s of millivolts. Care must be taken to avoid over-temperature conditions during this
validation exercise. Sustained current draw above VR TDC can easily result in component failure
and/or board damage.
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2222
RDSgmAVPVIDmanuf
kkVkVIDTOB ++=
AVPmaxAVP
R.IV =
TCripplemanuf
VVTOBTOB ++=