Voltage Regulator-Down (VRD) 10.0

Processor Voltage Requirements
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26 VRD Design Guide
through the VID table to a new voltage reference which can be any higher VID code, but is
generally the original reference VID.
Figure 9 illustrates processor-operating states as the VID level is lowered. The diagram assumes
steady state, maximum current during the transition for ease of illustration. In this figure, the
processor begins in a high-load condition. Upon entering D-VID, the processor will shift to a low
power state and stop executing code (sequence 1 => 2). After reaching state 2, the processor
encounters a brief delay to prepare for low power operation then re-initiates code, resulting in
current draw and a loadline IR drop to state 3. Sequencing from state 3 to 4 is a simplification of
the multiple steps from the original VID loadline window to the low-voltage VID window.
Transition from state 4 to state 5 is an example of a load change during normal operation in the
low voltage VID setting. Transition from a low to high VID reference follows the reverse
sequence
During a D-VID transition, Vcc must always reside above the minimum loadline of the current
VID setting (see Figure 9). The loadline values of each VID increment are required to match the
slope defined in Table 4. In addition, the voltage tolerance band and ripple specifications defined
in Table 4 Section 2.3 must be satisfied in this state. To expedite power reduction and processor
cooling, the VRD must lower the maximum Vcc value to reside within the low voltage VID
window within 50 microseconds of the final VID code transmission (see Figure 9 and Figure 10).
The VRD must respond to a transition from VID-low to VID-high by regulating the Vcc output to
the range defined by the new VID code within 50 microseconds of the final code transmission.
Note: The minimum VID is not constant among all processors; the value will vary with frequency and
standard VID settings. This results in numerous possible D-VID states. A simple and direct D-VID
validation method is defined at the end of this section.
During a D-VID event, the processor load may not be capable of absorbing output capacitor
energy when the VID reference is lowered. As a result, reverse current may flow into the AC-DC
regulator’s input filter, potentially charging the input filter to a voltage above the over voltage
value. Upon detection of this condition, the AC-DC regulator will react by shutting down the AC-
DC regulator supply voltage. The VRD and AC-DC filter must be designed to ensure this
condition does not occur. In addition, reverse current into the AC-DC regulator must not impair
the operation of the VRD, the AC-DC supply, or any other part of the system.
Under all functional conditions, including D-VID, the Vcc supply must satisfy loadline and
overshoot constraints to avoid data corruption, system lock-up events, or system blue-screen
failures.