Voltage Regulator-Down (VRD) 10.0

Processor Voltage Requirements

VRD Design Guide

2.10 Desktop VR Output Filter (REQUIRED)

Processor voltage regulators include an output filter to minimize transient noise on the Vcc rail.

Design analysis determined that the most cost efficient filter solution, for satisfying loadline

requirements, incorporates 680 µF aluminum-poly capacitors with 5 mΩ average ESR. High

frequency noise and ripple suppression is best minimized by 22 µF and/or 10 µF multi-layer

ceramic capacitors (MLCC’s). It is recommended to maximize the MLCC count in the socket

cavity to help suppress transients induced by microprocessor packaging hardware. Remaining

MLCC’s should be first placed adjacent to the socket edge in the region between the socket cavity

and the voltage regulator. If additional MLCC’s are needed to satisfy the loadline, they should be

placed on the socket edge that is opposite the VR adjacent edge.

The Dynamic VID mode of operation is directly impacted by the choice of bulk capacitors in the

output filter. It is recommended to minimize Vcc setting time during Dynamic VID operation to

hasten the speed of core power and temperature reduction. The speed of recovery is directly

related to the RC time constant of the output filter. To ensure adequate thermal recovery time, it is

recommended to design the output filter with a minimal amount of bulk capacitance with minimum

ESR, while providing a sufficient amount of decoupling to maintain loadline requirements. At this

time, 680µF aluminum poly capacitors with 5 mΩ average ESR have been identified as the

preferred solution.

It is common for a motherboard to support processors that require different VRD configurations

(see Table 4). In this case, the Vcc regulator design must meet the specifications of all processors

supported by that board. This requires the VRD to adopt an output filter design that satisfies the

lowest socket loadline value of all supported processors. For example, if a motherboard is to

support processors requiring 478_VR_CONFIG_A with a 1.24 mΩ loadline slope and

478_VR_CONFIG_D requiring a 1.5 mΩ loadline slope, the VRD output filter must have a

transient loadline value of 1.24 mΩ to satisfy the noise requirements of each processor.

Note: The VRD hardware must always be configured to each specific processor’s static loadline. For the

previous example, the VRD must recognize which processor is residing in the socket. If a

478_VR_CONFIG_A processor is detected, the static loadline must be set to 1.24 mΩ. If a

478_VR_CONFIG_A processor is replaced with a 478_VR_CONFIG_D processor, the VRD

hardware must detect the change and update the static loadline to 1.5 mΩ.

2.11 Shutdown Response (REQUIRED)

The VRD is to turn off the Vcc supply within 500ms upon receiving a processor driven OFF VID

code (see Table 18) or when the Output Enable signal is de-asserted (see section 3.1).