Voltage Regulator-Down (VRD) 10.0

R
4 VRD Design Guide
8
Motherboard Power Plane Recommendations (EXPECTED) .......................................... 49
8.1 Minimize Power Path DC Resistance................................................................... 49
8.2 Minimize Power Delivery Inductance.................................................................... 49
8.3 Four-Layer Boards................................................................................................ 49
8.4 Six-Layer Boards .................................................................................................. 50
Figures
Figure 1. Socket 478 Loadline Window for Design Configuration 478_VR_CONFIG_A
Presented As a Deviation from VID.
Socket Loadline = 1.24 mΩ, VR Tolerance Band = ±19 mV. .................................... 14
Figure 2. Socket 478 Loadline Window for Design Configuration 478_VR_CONFIG_B
Presented As a Deviation from VID.
Socket Loadline = 1.30 mΩ, VR Tolerance Band = ±25 mV. .................................... 15
Figure 3. Socket 478 Loadline Window for Design Configuration 478_VR_CONFIG_C
Presented As a Deviation from VID.
Socket Loadline = 1.50 mΩ, VR Tolerance Band = ±25 mV. .................................... 16
Figure 4. Socket 478 Loadline Window for Design Configuration 478_VR_CONFIG_D
Presented As a Deviation From VID.
Socket Loadline = 1.50 mΩ, VR Tolerance Band = ±19 mV. .................................... 17
Figure 5. Examples of High Volume Manufacturing Loadline Violations........................... 19
Figure 6. High Volume Manufacturing Compliant Loadline.............................................. 19
Figure 7. Power Sequence Block Diagram ....................................................................... 25
Figure 8. Power Sequence Timing Diagram ..................................................................... 25
Figure 9. Processor D-VID Loadline Transition States ..................................................... 27
Figure 10. D-VID Transition Timing States ....................................................................... 29
Figure 11. Overshoot and Undershoot During Dynamic VID Validation............................ 29
Figure 12. Graphical Representation of Overshoot Parameters....................................... 32
Figure 13. Processor Overshoot in High Volume Manufacturing...................................... 32
Figure 14. Example Socket Vcc Overshoot Waveform..................................................... 33
Figure 15: Example VRD Thermal Monitor Circuit Design................................................. 44
Figure 16. VID PWRGD Timing ........................................................................................ 47