Voltage Regulator-Down (VRD) 10.0

VccVID Voltage (PROPOSED)
R
VRD Design Guide
47
7 VccVID Voltage (PROPOSED)
The VccVID rail powers the processor VID buffers. This rail must power to regulation and assert an active-high
VID_PWRGD output according to the timing specified in Figure 8 and Figure 16 under the signaling conditions
defined in Table 21. There is no enable function for the VccVID regulator controller
Figure 16. VID PWRGD Timing
t
d1
t
r
VccVID
VID PWRGD
90%
90%
td2
V
t
Vol
t
d1
t
r
VccVID
VID PWRGD
90%
90%
10%
td2
V
t
Vol
Table 21. VccVID Specifications
Parameter Minimum Maximum Units
VccVID 1.14 1.26 Volts
VccVID current 150 - Milliamperes
VID PWRGD voltage 1.14 1.32 Volts
VID PWRGD Voh 1 VccVID Volts
VID PWRGD Vol -0.2 0.2 Volts
VID PWRGD de-assertion threshold, Vt 80% VccVID - Volts
VID PWRGD leakage - 50 Microamperes
Delay from VccVID to VID PWRGD, td1 1 10 Milliseconds
VID PWRGD rise time, tr - 150 Nanoseconds
VID PWRGD de-assertion delay, td2 - 1 Milliseconds