Voltage Regulator-Down (VRD) 10.0
R
VRD Design Guide 5
Tables
Table 1. Design Guideline Requirement Categories........................................................... 8
Table 2. Glossary ................................................................................................................ 8
Table 3. Socket Loadline Equations.................................................................................. 11
Table 4. Vcc Regulator Design Parameters...................................................................... 12
Table 5. Mapping of Intel Processors to VRD Configurations........................................... 13
Table 6. Socket 478 Loadline Window for Design Configuration 478_VR_CONFIG_A
Presented As a Deviation from VID.
Socket Loadline = 1.24 mΩ, VR Tolerance Band = ±19 mV. .................................... 14
Table 7. Socket 478 Loadline Window for Design Configuration 478_VR_CONFIG_B
Presented As a Deviation from VID.
Socket Loadline = 1.30 mΩ, VR Tolerance Band = ±25 mV. .................................... 15
Table 8. Socket 478 Loadline Window for Design Configuration 478_VR_CONFIG_C
Presented As a Deviation from VID.
Socket Loadline = 1.50 mΩ, VR Tolerance Band = ±25 mV. .................................... 16
Table 9. Socket 478 Loadline Window for Design Configuration 478_VR_CONFIG_D
Presented As a Deviation From VID.
Socket Loadline = 1.50 mΩ, VR Tolerance Band = ±19 mV. .................................... 17
Table 10. Intel
®
Processor Current Step Values for Transient Loadline Testing .............. 18
Table 11. Input Parameters for VRD TOB Calculation ..................................................... 21
Table 12. D-VID Validation Summary Table ..................................................................... 30
Table 13. Vcc Overshoot Terminology.............................................................................. 30
Table 14. Vcc Overshoot Specifications ........................................................................... 30
Table 15. Intel® Processor Current Release Values for Overshoot Testing..................... 31
Table 16. Output Enable Specifications ............................................................................ 37
Table 17. VID Signal Specifications .................................................................................. 37
Table 18. Voltage Identification (VID) Table ..................................................................... 38
Table 19. Power Good Specifications ............................................................................... 43
Table 20. Thermal Monitor Specifications......................................................................... 44
Table 21. VccVID Specifications ....................................................................................... 47