Voltage Regulator-Down (VRD) 10.1 Design Guide

Processor Vcc Requirements

Design Guide

Maximum overshoot is validated by monitoring the voltage across the recommended test lands

(defined in Section 2.2) while applying a current load release across the socket Vcc and Vss land

field. Amperage values for performing this validation under each VRD design configuration are

identified in Table 2-11. The platform voltage regulator output filter must be stuffed with a

sufficient quality and number of capacitors to ensure that overshoot stays above VID for a time no

longer than T

MAX

and never exceeds the maximum amplitude of VID+V

MAX

Measurements are to be taken using an oscilloscope with a 20 MHz bandwidth. Boards in

violation must be redesigned for compliance to avoid processor damage.

Table 2-11. Intel Processor Current Release Values for Overshoot Testing

VR Configuration Starting Current Ending Current Dynamic Current Step

775_VR_CONFIG_04A 5 A 60 A 55 A

775_VR_CONFIG_04B 5 A 100 A 95 A

775_VR_CONFIG_04C 5 A 94 A 89 A

775_VR_CONFIG_05A 35A 100A 65A

775_VR_CONFIG_05B 30A 125A 95A

To prevent processor damage, VRD designs should comply to overshoot specifications across the

full socket load line tolerance band window (see Section

2.2). When validating a system’s

overshoot, a single measurement is statistically insignificant and cannot represent the response

variation seen across the entire high volume manufacturing population of VRD designs. A typical

design may fit in the socket load line window; however designs residing elsewhere in the

tolerance band distribution may violate the Vcc overshoot specifications Figure 2-10 provides an

illustration of this concept. A typical board will have the Vcc zero current voltage (Vzc) centered

in the socket load line window at VID-TOB; for this example consider waveform A and assume

TOB is 20 mV. Now assume that the VRD has maximum overshoot amplitude of VOS_MAX =

50 mV above VID. Under this single case, the overshoot aligns with the specification limit and

there is zero margin to violation. Under manufacturing variation Vzc can drift to align with VID

(waveform B). This drift will shift the overshoot waveform by the same voltage level. Since

waveform A has zero overshoot amplitude margin, this increase in Vzc due to manufacturing drift

will yield a 20 mV overshoot violation which will reduce the processor life span. To address this

issue in validation, a voltage margining technique can be employed to ensure overshoot

amplitudes stay below a safe value. This technique translates the specification baseline from VID

to a VRD validation baseline of Vzc + VOS_MAX, which defines a test limit for specification

compliance across the full TOB range:

Equation 2-4. Overshoot Voltage Limit

< Vzc + VOS_MAX

This equation is to be used during validation to ensure overshoot is in compliance to

specifications across high volume manufacturing variation. In addition, the overshoot duration

must be reference to Vzc and cannot exceed this level by more than 25

µs.