Voltage Regulator-Down (VRD) 10.1 Design Guide

Power Sequencing (REQUIRED)

42 Design Guide

Table 4-1. Power Sequence Timing Parameters

Parameter Minimum Typical Maximum

TD1 1 ms - 50 ms

TD3 0 ms - -

TD4 0 ms - 500 ms

TOFF - - 500 ms

NOTES:

1. . Applicable to all designs

When the VRD has been enabled and is delivering current to the processor, it should shut down

power within 500 ms of receiving either a de-asserted Output Enable or an ‘OFF’ VID code

(111111 or 011111). After an 'OFF' VID event, the processor will not provide an updated VID

code to request current, so system power cycling must occur to restart the system.

Some VRD controllers sit idle (with no current delivered to the processor) waiting for a valid VID

code and do not shut down. This is not the preferred operation, but is a valid state that will not

cause functional failures.