Voltage Regulator-Down (VRD) 10.1 Design Guide

R
Design Guide 5
Figures
Figure 2-1. Socket Load Line Window for Design Configuration 775_VR_CONFIG_04A15
Figure 2-2. Socket Load Line Window for Design Configuration 775_VR_CONFIG_04B16
Figure 2-3. VRD Phase Orientation ..................................................................................19
Figure 2-4. Examples of High Volume Manufacturing Load Line Violations ....................21
Figure 2-5. High Volume Manufacturing Compliant Load Line.........................................21
Figure 2-6. Processor D-VID Load Line Transition States ............................................... 27
Figure 2-7. D-VID Transition Timing States......................................................................29
Figure 2-8. Overshoot and Undershoot during Dynamic VID Validation..........................29
Figure 2-9. Graphical Representation of Overshoot Parameters .....................................32
Figure 2-10. Processor Overshoot in High Volume Manufacturing ..................................32
Figure 2-11. Example Socket Vcc Overshoot Waveform .................................................33
Figure 4-1. Power-on Sequencing Block Diagram ...........................................................41
Figure 4-2. Power Sequence Timing Diagram.................................................................. 41
Figure 6-1. D-VID Bus Topology.......................................................................................46
Figure 9-1. VTTPWRGD Circuit........................................................................................54
Figure 9-2. Example VRD Thermal Monitor Circuit Design..............................................55
Figure 9-3. Processor Load Schematic for PROCHOT# AND FORCEPR# termination
(Single Load)..............................................................................................................57
Figure 10-1. Reference Board Layer Stack-up.................................................................60
Figure 10-2. Layer 1 Vcc Shape for Intel’s Reference Four-Layer Motherboard .............61
Figure 10-3. Layer 2 Vss Routing for Intel’s Reference Four-Layer Motherboard ...........61
Figure 10-4. Layer 3 Vss Routing for Intel’s Reference Four-Layer Motherboard ...........62
Figure 10-5. Layer 4 Vcc Shape for Intel’s Reference Four-Layer Motherboard .............62
Figure 11-1. Simplified Block Diagram Representing Electrical Connectivity for the VRD
on the Four-Layer Intel Reference Motherboard ....................................................... 65
Figure 11-2. Example Voltage Droop Observed at Node ‘N2’.......................................... 67
Figure 11-3. Current Step Observed Through I_PWL ...................................................... 68
Figure 11-4. Schematic Diagram for the Four-Layer Intel Reference Motherboard.........69
Figure 11-5. Node Location for the Schematic of Figure 11-4.......................................... 70
Figure 11-6. Schematic Representation of Bulk and High-Frequency Decoupling
Capacitors.................................................................................................................. 71
Figure 11-7. Schematic Representation of the LGA775 Socket.......................................72
Figure 11-8.
Current Load Step Profile for I_PWL from the Schematic of
Figure 11-7....73