Voltage Regulator-Down (VRD) 10.1 Design Guide

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Appendix: LGA775 Version 1 Pinmap

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Design Guide

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12 Appendix: LGA775 Version 1

Pinmap

Land Name Land #

Signal Buffer

Type Direction

A10# U6 Source Synch Input/Output

A11# T4 Source Synch Input/Output

A12# U5 Source Synch Input/Output

A13# U4 Source Synch Input/Output

A14# V5 Source Synch Input/Output

A15# V4 Source Synch Input/Output

A16# W5 Source Synch Input/Output

A17# AB6 Source Synch Input/Output

A18# W6 Source Synch Input/Output

A19# Y6 Source Synch Input/Output

A20# Y4 Source Synch Input/Output

A20M# K3 Asynch GTL+ Input

A21# AA4 Source Synch Input/Output

A22# AD6 Source Synch Input/Output

A23# AA5 Source Synch Input/Output

A24# AB5 Source Synch Input/Output

A25# AC5 Source Synch Input/Output

A26# AB4 Source Synch Input/Output

A27# AF5 Source Synch Input/Output

A28# AF4 Source Synch Input/Output

A29# AG6 Source Synch Input/Output

A3# L5 Source Synch Input/Output

A30# AG4 Source Synch Input/Output

A31# AG5 Source Synch Input/Output

A32# AH4 Source Synch Input/Output

A33# AH5 Source Synch Input/Output

A34# AJ5 Source Synch Input/Output

A35# AJ6 Source Synch Input/Output

A4# P6 Source Synch Input/Output

A5# M5 Source Synch Input/Output

A6# L4 Source Synch Input/Output

A7# M4 Source Synch Input/Output

A8# R4 Source Synch Input/Output

A9# T5 Source Synch Input/Output

ADS# D2 Common Clock Input/Output

ADSTB0# R6 Source Synch Input/Output

ADSTB1# AD5 Source Synch Input/Output