Voltage Regulator-Down (VRD) 10.1 Design Guide

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Appendix: LGA775 Version 1 Pinmap

R

76 Design Guide

Land Name Land #

Signal Buffer

Type Direction

AP0# U2 Common Clock Input/Output

AP1# U3 Common Clock Input/Output

BCLK0 F28 Clock Input

BCLK1 G28 Clock Input

BINIT# AD3 Common Clock Input/Output

BNR# C2 Common Clock Input/Output

BOOTSELECT Y1 Power/Other Input

BPM0# AJ2 Common Clock Input/Output

BPM1# AJ1 Common Clock Input/Output

BPM2# AD2 Common Clock Input/Output

BPM3# AG2 Common Clock Input/Output

BPM4# AF2 Common Clock Input/Output

BPM5# AG3 Common Clock Input/Output

BPRI# G8 Common Clock Input

BR0# F3 Common Clock Input/Output

BSEL0 G29 Power/Other Output

BSEL1 H30 Power/Other Output

BSEL2 G30 Power/Other Output

COMP0 A13 Power/Other Input

COMP1 T1 Power/Other Input

COMP2 G2 Power/Other Input

COMP3 R1 Power/Other Input

D0# B4 Source Synch Input/Output

D1# C5 Source Synch Input/Output

D10# B10 Source Synch Input/Output

D11# C11 Source Synch Input/Output

D12# D8 Source Synch Input/Output

D13# B12 Source Synch Input/Output

D14# C12 Source Synch Input/Output

D15# D11 Source Synch Input/Output

D16# G9 Source Synch Input/Output

D17# F8 Source Synch Input/Output

D18# F9 Source Synch Input/Output

D19# E9 Source Synch Input/Output

D2# A4 Source Synch Input/Output

D20# D7 Source Synch Input/Output

D21# E10 Source Synch Input/Output

D22# D10 Source Synch Input/Output

D23# F11 Source Synch Input/Output

D24# F12 Source Synch Input/Output

D25# D13 Source Synch Input/Output

D26# E13 Source Synch Input/Output

D27# G13 Source Synch Input/Output

D28# F14 Source Synch Input/Output

D29# G14 Source Synch Input/Output

D3# C6 Source Synch Input/Output