Voltage Regulator-Down (VRD) 10.1 Design Guide

Appendix: LGA775 Version 1 Pinmap
R
78 Design Guide
Land Name Land #
Signal Buffer
Type Direction
DEFER# G7 Common Clock Input
DP0# J16 Common Clock Input/Output
DP1# H15 Common Clock Input/Output
DP2# H16 Common Clock Input/Output
DP3# J17 Common Clock Input/Output
DRDY# C1 Common Clock Input/Output
DSTBN0# C8 Source Synch Input/Output
DSTBN1# G12 Source Synch Input/Output
DSTBN2# G20 Source Synch Input/Output
DSTBN3# A16 Source Synch Input/Output
DSTBP0# B9 Source Synch Input/Output
DSTBP1# E12 Source Synch Input/Output
DSTBP2# G19 Source Synch Input/Output
DSTBP3# C17 Source Synch Input/Output
FC10 E24 Power/Other Input
FC11 AM5 Power/Other Output
FC12 AM7 Power/Other Output
FC16 AN7 Power/Other Output
FC17 Y3 Power/Other Input
FC18 AE3 Power/Other Input
FC3 J2 Power/Other Input
FC4 T2 Power/Other Input
FC5 F2 Common Clock Input
FC7 G5 Source Synch Output
FERR#/PBE# R3 Asynch GTL+ Output
FORCEPR# AK6 Asynch GTL+ Input
GTLREF_SEL H29 Power/Other Output
GTLREF0 H1 Power/Other Input
GTLREF1 H2 Power/Other Input
HIT# D4 Common Clock Input/Output
HITM# E4 Common Clock Input/Output
IERR# AB2 Asynch GTL+ Output
IGNNE# N2 Asynch GTL+ Input
IMPSEL F6 Power/Other Input
INIT# P3 Asynch GTL+ Input
ITP_CLK0 AK3 TAP Input
ITP_CLK1 AJ3 TAP Input
LINT0 K1 Asynch GTL+ Input
LINT1 L1 Asynch GTL+ Input
LL_ID0 V2 Power/Other Output
LL_ID1 AA2 Power/Other Output
LOCK# C3 Common Clock Input/Output
MCERR# AB3 Common Clock Input/Output
MSID0 W1 Power/Other Input
MSID1 V1 Power/Other Input
PROCHOT# AL2 Asynch GTL+ Output or