Voltage Regulator-Down (VRD) 10.1 Design Guide

Appendix: LGA775 Version 1 Pinmap
R
Design Guide
79
Land Name Land #
Signal Buffer
Type Direction
Input/Output
PWRGOOD N1 Power/Other Input
REQ0# K4 Source Synch Input/Output
REQ1# J5 Source Synch Input/Output
REQ2# M6 Source Synch Input/Output
REQ3# K6 Source Synch Input/Output
REQ4# J6 Source Synch Input/Output
RESERVED A20
RESERVED AC4
RESERVED AE4
RESERVED AE6
RESERVED AH2
RESERVED C9
RESERVED D1
RESERVED D14
RESERVED D16
RESERVED E23
RESERVED E5
RESERVED E6
RESERVED E7
RESERVED F23
RESERVED F29
RESERVED G10
RESERVED B13
RESERVED J3
RESERVED N4
RESERVED N5
RESERVED P5
RESERVED G6
RESET# G23 Common Clock Input
RS0# B3 Common Clock Input
RS1# F5 Common Clock Input
RS2# A3 Common Clock Input
RSP# H4 Common Clock Input
SKTOCC# AE8 Power/Other Output
SMI# P2 Asynch GTL+ Input
STPCLK# M3 Asynch GTL+ Input
TCK AE1 TAP Input
TDI AD1 TAP Input
TDO AF1 TAP Output
TESTHI0 F26 Power/Other Input
TESTHI1 W3 Power/Other Input
TESTHI10 H5 Power/Other Input
TESTHI11 P1 Power/Other Input
TESTHI12 W2 Power/Other Input
TESTHI13 L2 Asynch GTL+ Input