VRM 9.0 DC-DC Converter Design Guidelines

This output should be capable of sinking up to 4mA, while maintaining a voltage of 0.4V or

lower. When the output is in the open state it should be capable of withstanding up to 5.5V.

Latch-up or damage cannot occur if the pull-up voltage on the system board is present with no

+12V input present.

VRM Power Good should remain low if the VRM is disabled by the Output Enable pin. System

designers need to provide appropriate logic on the system board to decode VRM Power Good,

VRM Enable, and system Power Good to prevent a false not-good condition (Power Good = low)

when the VRM is disabled.

The VRM should be able to detect a failure and de-assert PWRGD even if the output is within

the defined PWRGD range. It is sufficient for this purpose to detect whether all phases are

switching at their output inductors. The intention of this provision is to detect failures

independently when VRMs are sharing current to a common power plane in a multiple-processor

system.

1.6 VRM Present (VRM-pres) EXPECTED

This line is ground when the VRM is installed. The system board can use this signal to detect

when a VRM is installed in the system.

1.7 Efficiency PROPOSED

The efficiency of the VRM should be greater than 80% at maximum output current and input

voltage. It should not dissipate more power under any load condition than it does at maximum

output current and maximum input voltage.

1.8 Isolation PROPOSED

Isolation from input to output is optional. A transformer-based topology may have advantages

over a non-isolated buck converter: Over-voltage due to a shorted FET is eliminated, and duty

cycles can be optimized to simplify control or improve efficiency. Common ground between

input and output is required with an isolated topology.

1.9 Fault Protection

These are features built into the VRM to prevent damage to itself or the circuits it powers.

1.9.1 Over Voltage Protection EXPECTED

The VRM should provide over-voltage protection (OVP) by including a circuit, separate from the

voltage sense path, capable of shutting off the output drive when the output voltage rises beyond

Vtrip. If practical, the protection circuit should also enable a low-resistance path to ground such

that if the output transistor shorts to input power the output voltage will not rise above Vtrip. A

non-resettable or resettable fuse may be included in the input of the VRM for this function.