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Order Number: 304120

Intel NetStructure

MPCBL0010

Single Board Computer

Technical Product Specification

October 2006

Summary of content (198 pages)

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Intel NetStructure® MPCBL0010 Single Board Computer Technical Product Specification October 2006 Order Number: 304120
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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—MPCBL0010 Contents 1.0 Introduction ............................................................................................................ 12 1.1 Document Organization...................................................................................... 12 1.2 Glossary .......................................................................................................... 13 2.0 Feature Overview ....................................................................................................
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MPCBL0010— 3.8.2.1 3.9 Synchronizing BIOS Image and Settings from FWH0 (Main) to FWH1 (Backup)33 3.8.2.2 Copying BIOS.bin from the SBC ..................................................34 3.8.2.3 Saving BIOS.bin to the SBC ........................................................34 3.8.2.4 flashlnx Command Line Options .................................................35 3.8.3 IPMC Firmware Updates...........................................................................35 3.8.3.
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—MPCBL0010 7.0 BIOS 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 Setup .............................................................................................................. 62 Introduction ..................................................................................................... 62 Main Menu ....................................................................................................... 62 Advanced Menu.......................................................................................
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MPCBL0010— 10.9 10.10 10.11 10.12 10.13 10.14 10.8.2 Board Device Channel Port Selection Identifiers ........................................ 131 10.8.2.1 SetBoardDeviceChannelPortSelection ......................................... 132 10.8.2.2 GetBoardDeviceChannelPortSelection ......................................... 133 10.8.2.3 GetBoardDevicePossibleSelection............................................... 133 10.8.3 Set Control State ..................................................................
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—MPCBL0010 11.9 11.8.2.3 Start an SOL Session............................................................... 158 11.8.2.4 Checking SOL Configuration ..................................................... 158 11.8.2.5 Ending an SOL Session ............................................................ 159 Operating Systems for SOL Client (ipmitool) ....................................................... 160 12.0 Telecom Clock ...................................................................................
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MPCBL0010— 17.3 17.4 Sales Assistance .............................................................................................. 183 Product Code Summary .................................................................................... 183 18.0 Certifications ......................................................................................................... 184 19.0 Agency Information—Class B ................................................................................. 185 19.
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—MPCBL0010 Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Supported Memory Configurations.............................................................................. 18 Jumper Definitions ................................................................................................... 26 Suggested Method of BIOS Image Synchronization prior to BIOS Upgrade .......................
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MPCBL0010— 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 OS Load Timeout Timer Sub-Menu ..............................................................................85 Security Menu ..........................................................................................................85 Chipset Menu .............................................................................
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—MPCBL0010 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 Hardware Sensors .................................................................................................. 117 OEM Sensor Types ................................................................................................. 120 OEM Event/Reading Type .....................................................
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MPCBL0010— Revision History Date Revision September 2006 002 March 2006 001 Description Updated to include the following: -- new Chapter 11, “Serial over LAN” -- CMOS_CLR jumper change -- new sensor threshold data -- change to sensor name, Temp CPLD Area -- new section 3.8.2.1 for other flashInx command options -- new information about using ipmitool in section 3.8.3 -- corrected duplicate section names in 4.3.2 and 4.3.3 -- new note in section 6.
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MPCBL0010—Introduction 1.0 Introduction 1.1 Document Organization This document provides technical specifications related to the Intel NetStructure® MPCBL0010 Single Board Computer (SBC). The MPCBL0010 SBC is designed following the standards of the Advanced Telecommunications Compute Architecture (AdvancedTCA*) Design Guide for high availability, switched network computing. This document is intended for support during system product development and while sustaining a product.
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Introduction—MPCBL0010 Chapter 13.0, “Maintenance” includes supervision and diagnostics information. Chapter 14.0, “Thermals” describes pressure drop curves versus the flow rate in accordance with PICMG 3.0 Specification.. Chapter 15.0, “Component Technology” lists the major components used on the MPCBL0010. Chapter 16.0, “Warranty Information” provides warranty information for Intel NetStructure® products. Chapter 17.0, “Customer Support” provides information on how to contact customer support.
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MPCBL0010—Introduction IBA Intel® Boot Agent. The Intel Boot Agent is a software product that allows your networked client computer to boot using a program code image supplied by a remote server. IDE Integrated Device Electronics. Common, low-cost disk interface. IPMB Intelligent Platform Management Bus. Physical two-wire medium to carry IPMI. IPMC Intelligent Platform Management Controller. ASIC on baseboard responsible for low-level system management.
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Feature Overview—MPCBL0010 SBC 2.0 Feature Overview 2.1 Application The Advanced Telecommunications Compute Architecture (AdvancedTCA*) standards define open architecture modular computing components for a carrier-grade, communications network infrastructure. The goals of the standards are to enable blade-based modular platforms to be: • cost effective • high-density • high-availability • scalable These systems use a fabric I/O network for connecting multiple, independent processor boards, I/O nodes (e.
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MPCBL0010 SBC—Feature Overview Figure 1. MPCBL0010 Block Diagram Firmware FirmwareHub Hub (FWH0) (FWH0) LEDs LEDs 33 MHz LPC (4MB/s) Two Two 240-pin 240-pinDIMM DIMM Sockets Sockets DDR2 DDR2400 400 Registered Registered DIMMs DIMMs USB USBPort Port 800 MHz LV LV Intel® Intel®Xeon™ Xeon™ 2.8 2.8GHz GHz On-board On-board Power Power Supplies Supplies and andHot Hot Swap Swap Circuitry Circuitry HI 1.
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Feature Overview—MPCBL0010 SBC • Intel® 6700PXH 64-bit PCI Hub A brief overview is provided here and detailed component information can be found in each device’s respective documentation. 2.2.2.
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MPCBL0010 SBC—Feature Overview Note: Two 25-degree 240-pin DIMMs theoretically support memory configurations up to 8 GBytes of PC2-3200 registered DDR2-400 SDRAM, but only memory configurations of 2 GBytes and 4 GBytes have been validated. Table 1.
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Feature Overview—MPCBL0010 SBC The hardware may support an assignable decode space; however, the BIOS will set this space prior to handing it over to the OS. It is not expected that the OS will move the location of these timers once the space is set by the BIOS. In the 6300ESB ICH, one timer block is implemented. The timer block has one counter and three timers (comparators). Various capabilities registers indicate the number of timers and the capabilities of each. 2.2.4.3.
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MPCBL0010 SBC—Feature Overview In addition to the PCI Express connections to the AdvancedMC slots, SATA and AdvancedTCA zone 2 telecom clock signals are also connected to each AdvancedMC slot. The MPCBL0010 SBC features a two-channel bus master PCI SATA interface through the 6300ESB ICH. Each channel supports one device and is available through the AdvancedMC module slots. Each of these x8 PCI Express ports routed to the AdvancedMC connectors can train with a link width of x8, x4, or x1.
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Feature Overview—MPCBL0010 SBC 2.2.6.2 FWH1 (Backup/Recovery BIOS) The FWH1 firmware hub stores the recovery BIOS. In the event of a checksum failure on the main BIOS operational code, the BIOS requests the BMC to switch firmware hubs, so that the board can boot up from FWH1 for recovery. 2.2.6.3 Flash ROM Backup Mechanism The on-board Intelligent Platform Management Controller (IPMC) manages which of the two BIOS flash ROMs is used during the boot process.
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MPCBL0010 SBC—Feature Overview Current values here indicate the maximum that can be delivered by design and do not reflect the current actually provided on the MPCBL0010 SBC. Additionally, each converter has design margin. The maximum current that can be drawn by the SBC in operation is 200 Watts, conforming with the AdvancedTCA 3.0 specification. 2.2.7.4 Processor Voltage Regulator Module (VRM) The Voltage Regulator Module (VRM) provides core power to the Low Voltage Xeon processor.
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Feature Overview—MPCBL0010 SBC Control and status registers are implemented in the FPGA. States are synchronized between the FPGA and the PLD through a 33MHz full-duplex synchronous serial link. The FPGA being attached to the main processor as well as the IPMC allows for flexibility, and accesses to the control/status registers are simple and fast. The PLL and clock buffers are not powered in the suspend well and stop working when the SBC is powered down.
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MPCBL0010 SBC—Feature Overview Figure 2. AdvancedMCA Direct Connect Switch Block Diagram ! " 2.2.11 AdvancedTCA Compliance The MPCBL0010 SBC conforms to the following specifications: — PICMG 3.0 R2.0 — PICMG 3.1 R1.0 (Ethernet/Fiber Channel over AdvancedTCA) — AdvancedMC.0 R1.0 — AdvancedMC.1 R1.0 — AdvancedMC.2 R1.0 — AdvancedMC.3 R1.0 — ACPI R1.
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Operating the Unit—MPCBL0010 SBC 3.0 Operating the Unit 3.1 Jumpers The MPCBL0010 SBC contains several jumper posts that allow the user to configure certain options not configurable through the BIOS setup utility. Figure 3 shows the placement of the MPCBL0010 SBC jumpers. The MPCBL0010 SBC is shipped preconfigured and jumper positions do not generally need to be altered. Figure 3. Jumpers Figure 4 shows the jumper locations on the SBC. Table 2 gives definitions for each of these jumpers.
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MPCBL0010 SBC—Operating the Unit 1 Jumper/Connector Locations Figure 4. 4 B5440-02 Table 2. Jumper Definitions Function with Jumper Present (On) Name Function with Jumper Removed (Off) JP3 VT100 Mode Enabled (default) Disabled JP5 Clear CMOS Clear CMOS Normal operation (default) JP6 IPMC Override for MPCBL0010 SBC (posts 1-2) SBC Activation Override.
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Operating the Unit—MPCBL0010 SBC Table 2. Jumper Definitions (Continued) Function with Jumper Present (On) Name Function with Jumper Removed (Off) IPMC is completely disabled and always in RESET mode. JP7 IPMC Override (posts 3-4) Normal IPMC operation (default) JP8 FPGA Config User PROM (default) Factory PROM (for manufacturing purposes only) JP10 Test Mode Test Mode (for manufacturing purposes only).
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MPCBL0010 SBC—Operating the Unit 3.3 Installing Memory DDR2-400 DIMMs must be installed in matched pairs. Memory DIMMs of 1 GBytes or 2 GBytes are supported for a total of 2 Gbytes (2x1 Gbyte) or 4 Gbytes (2x2 Gbytes) of system memory. Matched pairs in this case means a pair of DIMMs equal in speed, density, and technology. Preferably, the same vendor and part number for both pairs. See the MPCBL0010 SBC Compatibility Report on the Intel web site for a list of approved memory part numbers and vendors.
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Operating the Unit—MPCBL0010 SBC 3. Insert two matched pair DIMMs. Warning: Using excessive force to install memory can damage the DIMM socket and/or circuit board. Figure 8. Memory Installed 4. Reinstall the cover. 5. Reinstall the six cover screws. Note: Should any of the cover screws get lost in this process, the specifcations for them are: • Flat head Phillips screws countersunk M2.5 x 3.4 • Steel with Precote* 80 (pink) coating all around 3.
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MPCBL0010 SBC—Operating the Unit 3.4.1 Chassis Installation 1. Insert the MPCBL0010 SBC into the chassis with the latching cams at a 75º angle. This will set the latching cams into the installation position. Move the latching cam by pressing the handle inward to free the latching cam for rotation. 2. While holding inward pressure on the handle, slide the MPCBL0010 SBC into the chassis. Begin rotating the latching cam back to 0º allowing the cam to assist with insertion.
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Operating the Unit—MPCBL0010 SBC Section 3.4.1). To rotate the cam, the handle must be pushed in towards the SBC when moving the handle up or down. 1. Rotate the lower handle to the horizontal position, and push in to disengage the Hot Swap switch (position 1a to 1b). Wait for the Hot Swap LED on the faceplate to turn solid blue. 2.
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MPCBL0010 SBC—Operating the Unit 4. Simultaneously push both handles in again and rotate until the handles are at their farthest point of travel. Repeat this process until the SBC faceplate is clear of the chassis. At this point the SBC can be removed from the chassis. 3.5 AdvancedMC Module Installation and Extraction To install or remove an AdvancedMC* module into the MPCBL0010 SBC, simply move the SBC handle from the vertical to the horizontal position.
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Operating the Unit—MPCBL0010 SBC You can download software updates for the MPCBL0010 SBC from this Intel web site: http://www.intel.com/design/telecom/products/cbp/atca/9445/overview.htm 3.8.1 BIOS Updates At times, new BIOS images will be released to the Intel web site which may add additional features to the SBC. The BIOS update release package contains the BIOS ROM image, as well as the flash update utilities.
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MPCBL0010 SBC—Operating the Unit Table 3. Suggested Method of BIOS Image Synchronization prior to BIOS Upgrade FW H0 Image N+1 • ./flashlnx –b Pxx-xxxx FW H1 Image N Note: 3.8.2.2 • • When this command is initiated, the FWH0 image will be updated to the latest version (Image N+1). The latest version of the BIOS will take effect after the user initiates a reset. If a checksum error is detected on FWH0 after a reboot, it will automatically switch to FWH1 and regain normal operation.
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Operating the Unit—MPCBL0010 SBC 3.8.2.4 flashlnx Command Line Options Table 4 lists the command line parameter switches and features supported by the BIOS flash utility. Table 4. 3.8.
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MPCBL0010 SBC—Operating the Unit # ipmitool fwum download .bin # ipmitool fwum upgrade .bin 4. To verify that the upgrade worked properly, run the following command: # ipmitool fwum status The output of this command should show the “last known good” version to be the same as the version just upgraded to. The “previous good” version should show the previous version before the upgrade. 5.
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Specifications—MPCBL0010 SBC 4.0 Specifications This section defines the Intel NetStructure® MPCBL0010 Single Board Computer operating and storage environments. It also documents the procedures followed to determine the reliability of the MPCBL0010 SBC. 4.1 Mechanical Specifications 4.1.1 Board Outline The MPCBL0010 SBC form factor is mechanically compliant to PICMG 3.0 specification of 322.25 mm x 280.00 mm (12.687" x 11.024"). The board pitch is 6HP, and the PCB thickness is 2.0 mm (+/-0.2 mm). 4.
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MPCBL0010 SBC—Specifications Table 5. Environmental Specifications (Sheet 2 of 2) Altitude 4000 m (13123 ft.) Note: May require additional cooling above 1800 m (5905 ft.) Operating Storage 15000 m (49212 ft.) Operating Sine sweep: • 5 to 100 Hz: 1G @ 0.25 Octave/minute • 100 to 500 Hz: 1G @ 1 Octave/minute Random profile: • 5 Hz @ 0.01 g2 /Hz to 20 Hz @ 0.02 g2 /Hz (slope up) • 20 Hz to 500 Hz @ 0.02 g2 /Hz (flat) • 3.13 g RMS, 10 minutes per axis for all 3 axes Storage 5 to 50 Hz: 0.5G @ 0.
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Specifications—MPCBL0010 SBC 4.3.1.3 General Notes • Method I, Case I = Based on parts count. Equipment failure is estimated by totaling device failures rates and quantities used. • Quality Level II = Devices purchased to specifications, qualified devices, vendor lotto-lot controls for AQLs and DPMs. • Where available, direct component supplier predictions or actual FIT rates have been used. • The SBC MTBF does not include addition of the AdvancedMC cards.
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MPCBL0010 SBC—Connectors and LEDs 5.0 Connectors and LEDs Connectors along the rear edge of AdvancedTCA* server blades are divided into three distinct zones, as described in Section 2.3 of the PICMG 3.0 specification: • Zone 1 for system management and power distribution • Zone 2 for data fabric • Zone 3 for the rear transition module (not used on the MPCBL0010 SBC) As shown in Figure 10, the MPCBL0010 SBC includes several connectors to interface with application-specific devices.
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Connectors and LEDs—MPCBL0010 SBC 1 Connector Locations Figure 10. 4 B5440-02 Table 10.
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MPCBL0010 SBC—Connectors and LEDs Figure 11. Front Panel B5444-01 Table 11. Front Panel Connector Assignments Front Panel Connectors Description J3 10/100 Ethernet Debug Port J4 USB 2.
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Connectors and LEDs—MPCBL0010 SBC 5.1 Backplane Connectors 5.1.1 Power Distribution Connector (P10) Zone 1 consists of P10, a blue 34-pin Positronic* header connector that provides the following signals: • Two -48 VDC power feeds (four signals each; eight signals total) • Two IPMB ports (two signals each, four signals total) • Geographic address (eight signals) • 5.
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MPCBL0010 SBC—Connectors and LEDs Table 12.
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Connectors and LEDs—MPCBL0010 SBC Figure 13. Data Transport Connector (Zone 2) J23 HG FG DG BG HG FE DC BA 1 2 3 4 5 6 7 8 9 10 B0899-01 The following naming convention describes the signals on this connector. Signal direction is defined from the perspective of the MPCBL0010 SBC.
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MPCBL0010 SBC—Connectors and LEDs Table 13.
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Connectors and LEDs—MPCBL0010 SBC 5.2 On-Board Connectors 5.2.1 POST Code Connector (J13) The 8-bit content of I/O address 80h is serialized into a proprietary protocol and the output sent to the J13 connector. In manufacturing, a display board is used to deserialize and display the POST code value on 7-segment LEDs modules. Table 15. 5.2.
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MPCBL0010 SBC—Connectors and LEDs 5.3 Front Panel Connectors 5.3.1 Ethernet 10/100 Debug Connector (J3) A single Ethernet port interface is provided on the front edge of the card using an RJ-45 style shielded connector (Tyco* RJ714-CL2). This port can be used for debug or management. See Figure 10 for its position on the board. Note: When using the Ethernet 10/100 Debug Connector, you must use shielded category 5 cabling. Figure 14. Ethernet 10/100 Debug Connector Table 16.
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Connectors and LEDs—MPCBL0010 SBC 5.3.2 USB Connector (J4) The MPCBL0010 SBC has one USB connector that supports 2.0 and 1.1 USB. USB connector J4 is available at the front panel. See Figure 10for its position on the board. Figure 15. USB Connector (J4) Table 18. USB Connector (J4) Pin Assignments 5.3.3 Pin Signal 1 +5 V 2 -DATA 3 +DATA 4 GND Serial Port Connector (J5) A single serial port interface is provided on the front edge of the card using an RJ-45 style shielded connector.
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MPCBL0010 SBC—Connectors and LEDs Table 19. Serial Port Connector (J5) Pin Assignments Pin Signal 1 RTS 2 DTR 3 TXD 4 GND 5 GND 6 RXD 7 DSR 8 CTS Figure 17. DB-9 to RJ-45 Pin Translation 5.3.4 AdvancedMC* Connectors (J18, J19) There is a single AMC B+ connector for each AdvancedMC slot. Connector J18 corresponds to AMC designator B1. Connector J19 corresponds to AMC designator B2. The connectors and pinouts are defined by the industry standard specifications AMC.0 R1.0, AMC.1 R1.
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MPCBL0010 SBC—Connectors and LEDs Table 20.
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MPCBL0010 SBC—Connectors and LEDs Figure 18. AdvancedMC* Connector Caution: Do not ship the MPCBL0010 SBC with third party AdvancedMC modules installed. Damage that occurs to the MPCBL0010 SBC during shipment from AdvancedMC modules installed is not covered by the MPCBL0010 SBC product warranty. 5.4 LEDs The MPCBL0010 SBC provides several LEDs to indicate status. The LEDs can be driven to display red, green or amber color.
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Connectors and LEDs—MPCBL0010 SBC Figure 19. Front Panel LEDs (Option 1) Figure 20.
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MPCBL0010 SBC—Connectors and LEDs Table 21. Front Panel LED Descriptions (Sheet 1 of 2) LED Function H/S Hot Swap (AdvancedTCA-Blue). The LED’s default IPMC behavior can be overridden with AdvancedTCA FRU LED Control commands. Off / Blue OOS HLT Out of Service (AdvancedTCA-LED1). Amber: The IPMC is not responding. Amber-blink: The IPMC firmware is being upgraded. Off: The IPMC is running OK. The LED’s default IPMC behavior can be overridden with AdvancedTCA FRU LED Control commands.
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Connectors and LEDs—MPCBL0010 SBC Table 21. Front Panel LED Descriptions (Sheet 2 of 2) LED Function This LED has two functions. The LED will display POST codes in the event the SBC fails to boot. Once the SBC has booted and passed BIOS POST, this LED will indicate hard disk activity. HDD Hard Disk activity Green-blink: Activity POST Codes. Off / Green / Red / Amber See Section , “” on page 55 for more detail. IPMC Status. Slow Blink Green: IPMC Heartbeat.
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MPCBL0010 SBC—Connectors and LEDs operating system launches. If the boot sequence fails or the CPU hangs, the HDD (POST) LED will remain operational in POST code mode and repeat indefinitely the last POST code blink sequence as defined below: 1. Blink simultaneously amber and green one time: start of the sequence. 2. Blink amber 0-15 times while green stays off. 3. Blink green 0-15 times while amber stays off. 4. Repeat the sequence (see step 1).
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BIOS Features—MPCBL0010 SBC 6.0 BIOS Features 6.1 Introduction The MPCBL0010 SBC uses an Intel/AMI* BIOS, which is stored in flash memory and updated using a disk-based program. In addition to the BIOS and BIOS setup program, the flash memory contains POST and Plug and Play support. The BIOS displays a message during POST identifying the type of BIOS and a revision code. Refer to the Specification Update on the Documentation tab of the MPCBL0010 SBC web site at http://www.intel.
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MPCBL0010 SBC—BIOS Features 6.5 Legacy USB Support Legacy USB support enables USB devices such as keyboards, mice, and hubs to be used even when the operating system’s USB drivers are not yet available. Legacy USB support is used to access the BIOS Setup program and install an operating system that supports USB. Legacy USB support is set to Enabled by default. Note: Legacy USB support is for keyboards, mice and hubs only.
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BIOS Features—MPCBL0010 SBC • 5th Boot Device: IBA1 - Intel® Boot Agent (IBA) 0308 • 6th Boot Device: IBA2 - Intel® Boot Agent (IBA) 0311 • 7th Boot Device: IBA2 - Intel® Boot Agent (IBA) 0310 Note: Additional boot devices may appear in the above list if there are other bootable devices connected to the board (for example, USB devices or AdvancedMC devices). 6.7.1 CD-ROM and Network Boot Booting from CD-ROM is supported in compliance with the “El Torito” bootable CD-ROM format specification.
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MPCBL0010 SBC—BIOS Features • If both the supervisor and user passwords are set, users can enter either the supervisor password or the user password to access setup. Access to setup corresponds to which password is entered. • Setting the user password restricts who can boot the computer. The password prompt is displayed before the computer is booted. If only the supervisor password is set, the computer boots without asking for a password.
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BIOS Features—MPCBL0010 SBC Table 24.
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MPCBL0010 SBC—BIOS Setup 7.0 BIOS Setup 7.1 Introduction The MPCBL0010 SBC BIOS is based on AMIBIOS8*. The BIOS Setup program can be used to view and change the BIOS settings for the SBC. The BIOS Setup program is accessed by pressing the ~~key (or F4 on a remote keyboard) after the Power-On Self-Test (POST) begins and before the operating system boot begins. Table 25 lists the BIOS Setup program menu features. Table 25.~~
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BIOS Setup—MPCBL0010 SBC Table 27 describes the Main menu. This menu reports processor and memory information and is used for configuring the system date and system time. Table 27. Main Menu Feature 7.3 Options Description BIOS ID Version Build Date ID Displays the BIOS version, build date, and ID. PLD Information FPGA Version Programmable Logic Device Version Information. Processor Type Speed Count Reports processor type, speed, and count.
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MPCBL0010 SBC—BIOS Setup Table 28. Advanced Menu Feature 7.3.1 Options Description CPU Configuration Select to display sub-menu Display CPU details, Enable/Disable Hyper-Threading** technology. IDE Configuration Select to display sub-menu Display the primary IDE master and primary IDE slave drive. SuperIO Configuration Select to display sub-menu Set parallel port address/interrupt.
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BIOS Setup—MPCBL0010 SBC Main Advanced PCIPnP Boot Security Chipset Exit Remote Access Configuration IPMI Configuration USB Configuration Table 29 shows the sub-menu options for configuring the CPU. Table 29. CPU Configuration Sub-Menu Feature Description Manufacturer Display CPU Manufacturer. Brand String Display CPU Brand String. Frequency Display CPU Frequency. FSB Speed Displays Front Side Bus Speed. Cache L1 Displays L1 Cache size. Cache L2 Displays L2 Cache size.
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MPCBL0010 SBC—BIOS Setup Main Advanced PCIPnP Boot Security Chipset Exit Event Log Configuration MPS Configuration ATCA Channel Routing (PICMG) On-board Devices Configuration PCI Express Configuration Remote Access Configuration IPMI Configuration USB Configuration Table 30 shows the IDE configuration options. Table 30. IDE Configuration Sub-Menu Feature Options Description IDE Configuration Disabled P-ATA Only S-ATA Only P-ATA & S-ATA Selects IDE mode.
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BIOS Setup—MPCBL0010 SBC Table 30. IDE Configuration Sub-Menu (Continued) Feature Description Hard Disk Write Protect Disabled Enabled Enable/Disable Hard Disk device write protection. This is effective only if the device is accessed through BIOS. IDE Detect Time Out 0 5 10 15 20 25 30 35 Select the time out value for detecting ATA/ATAPI device(s). Note: 7.3.2.1 Options Bold text indicates default setting.
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MPCBL0010 SBC—BIOS Setup Table 31. IDE Master/Slave Sub-Menu (Continued) Feature DMA Mode Auto SWDMA0 SWDMA1 SWDMA2 MWDMA0 MWDMA1 MWDMA2 UDMA0 UDMA1 UDMA2 UDMA3 UDMA4 32 Data Transfer Disabled Enabled Note: 7.3.3 Options Description Select DMA Mode: Auto: Auto detected SWDMAn: SingleWordDMAn MWDMAn: MultiWordDMAn UDMAn: UltraDMAn Enable/Disable 32-bit Data Transfer. Bold text indicates default setting.
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BIOS Setup—MPCBL0010 SBC 5 Table 32. SuperIO Configuration Sub-Menu Feature Description ICH Serial Port1 Address Disabled 3F8/IRQ4 2F8/IRQ3 3E8/IRQ4 2E8/IRQ3 Set serial port 1 address and interrupt. ICH Serial Port2 Address Disabled 3F8/IRQ4 2F8/IRQ3 3E8/IRQ4 2E8/IRQ3 Set serial port 2 address and interrupt. PLD POD Devicer Disabled Enabled Enable to use on-board LPT port to program PLD with POD device.
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MPCBL0010 SBC—BIOS Setup Main Advanced PCIPnP Boot Security Chipset Exit Remote Access Configuration IPMI Configuration USB Configuration Table 33 shows ACPI configuration options. Table 33. ACPI Configuration Sub-Menu Feature 7.3.4.1 Options Description Advanced ACPI Configuration Configure advanced ACPI options. Chipset ACPI Configuration Configure ACPI chipset options.
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BIOS Setup—MPCBL0010 SBC Table 35. Chipset ACPI Configuration Sub-Menu Feature APIC ACPI SCI IRQ Note: 7.3.5 Options Description Disabled Enabled Enable/Disable APIC ACPI SCI interrupt. Bold text indicates default setting. System Management Sub-Menu To access this sub-menu, select Advanced on the menu bar, then System Management.
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MPCBL0010 SBC—BIOS Setup Table 36. System Management Sub-Menu Feature 7.3.6 Options Description Board Product Name Displays Board Product Name. Board Serial Number Displays Board Serial Number. Board Part Number Displays Board Part Number. Product Name Displays Product Name. Product Part/Model Displays Product Part/Model. Product Version Number Displays Product Version Number. Product Serial Number Displays Product Serial Number. IPMI Version Displays IPMI Version.
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BIOS Setup—MPCBL0010 SBC Table 37. Event Log Configuration Sub-Menu Feature Options Description View Event Log View all unread events. Mark all events as read Option to Mark all events as read. Clear Event Log Discard all events in the log. ECC Event Logging Disabled Enabled Enable/Disable fatal error event logging. Hub Interface Event Logging Disabled Enabled Enable/Disable Hub Interface error logging. System Bus Event Logging Disabled Enabled Enable/Disable System Bus error logging.
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MPCBL0010 SBC—BIOS Setup 7.3.7 MPS Configuration Sub-Menu To access this sub-menu, select Advanced on the menu bar, then MPS Configuration.
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BIOS Setup—MPCBL0010 SBC MPS Configuration ATCA Channel Routing (PICMG) On-board Devices Configuration PCI Express Configuration Remote Access Configuration IPMI Configuration USB Configuration Table 40 shows MPS Configuration options. Table 40. AdvancedTCA Channel Routing (PICMG) Sub-Menu Feature Options Displays port state based on E-key granting from the AdvancedTCA shelf manager.
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MPCBL0010 SBC—BIOS Setup Main Advanced PCIPnP Boot Security Chipset Exit CPU Configuration IDE Configuration SuperIO Configuration ACPI Configuration System Management Event Log Configuration MPS Configuration ATCA Channel Routing (PICMG) On-board Devices Configuration PCI Express Configuration Remote Access Configuration IPMI Configuration USB Configuration Table 41 shows On-board Devices Configuration options. Table 41.
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BIOS Setup—MPCBL0010 SBC Main Advanced PCIPnP Boot Security Chipset Exit CPU Configuration IDE Configuration SuperIO Configuration ACPI Configuration System Management Event Log Configuration MPS Configuration ATCA Channel Routing (PICMG) On-board Devices Configuration PCI Express Configuration Remote Access Configuration IPMI Configuration USB Configuration Table 43 shows PCI Express configuration options. Table 43.
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MPCBL0010 SBC—BIOS Setup Main Advanced PCIPnP Boot Security Chipset Exit System Management Event Log Configuration MPS Configuration ATCA Channel Routing (PICMG) On-board Devices Configuration PCI Express Configuration Remote Access Configuration IPMI Configuration USB Configuration Table 44 shows remote access configuration options. Table 44. Remote Access Configuration Sub-Menu Feature Options Description Remote Access Disabled Enabled Enable / Disable Remote Access function.
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BIOS Setup—MPCBL0010 SBC Main Advanced PCIPnP Boot Security Chipset Exit CPU Configuration IDE Configuration SuperIO Configuration ACPI Configuration System Management Event Log Configuration MPS Configuration ATCA Channel Routing (PICMG) On-board Devices Configuration PCI Express Configuration Remote Access Configuration IPMI Configuration USB Configuration Table 45 shows the IPMI configuration options. Table 45.
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MPCBL0010 SBC—BIOS Setup Table 46. LAN Configuration Sub-Menu Feature Description Gateway Address Gateway address used by SOL MAC Address This is a read-only field that displays the MAC address of the network interface that will be used for SOL Note: 7.3.13 Options Bold text indicates default setting. USB Configuration Sub-Menu To access this sub-menu, select Advanced on the menu bar, then USB Configuration.
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BIOS Setup—MPCBL0010 SBC Table 47. USB Configuration Sub-Menu (Continued) Feature Description USB 2.0 Controller Mode FullSpeed HiSpeed Configures USB 2.0 for HiSpeed (480 Mbps), or FullSpeed (12 Mbps). BIOS EHCI Hand-Off Disabled Enabled Enables work-around for operating systems without EHCI hand-off support. Note: 7.3.13.1 Options Bold text indicates default setting. USB Mass Storage Device Configuration Table 48 shows USB Mass Storage Device Configuration options. Table 48.
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MPCBL0010 SBC—BIOS Setup 7.5 Boot Menu To access this menu, select Boot from the menu bar at the top of the screen. Main Advanced PCIPnP Boot Security Chipset Exit Boot Settings Configuration Boot Device Priority Hard Disk Drives OS Load Timeout Timer Table 50 shows options for setting the boot features and boot sequence. Table 50. Boot Menu Feature 7.5.1 Options Description Boot Settings Configuration Select to display sub-menu Set boot options.
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BIOS Setup—MPCBL0010 SBC Table 51. Boot Settings Configuration Sub-Menu (Sheet 2 of 2) Feature Description Bootup Num-Lock Off On Set power-on state for num-lock. PS/2 Mouse Support Disabled Enabled Auto Set support for PS/2 mouse. Wait For ‘F1’ If Error Disabled Enabled Disable/enable waiting for F1 key to be pressed if error occurs. Hit ‘DEL’ Message Display Disabled Enabled Display “Press DEL to run Setup” in POST.
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MPCBL0010 SBC—BIOS Setup Table 52. Boot Device Priority Sub-Menu (Continued) Feature Description 4th Boot Device Displays detected boot devices Set the fourth boot device. 5th Boot Device Displays detected boot devices Set the fifth boot device. Note: 1. 2. 3. 4. 5. 6. 7.5.3 Options A device only shows as an option if it is installed and detected by the BIOS during boot.
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BIOS Setup—MPCBL0010 SBC Table 54 Table 54. OS Load Timeout Timer Sub-Menu Feature OS Load Action Note: 7.6 Options Description Disabled Reset System Power Down Power Cycle Specifies the action to take upon timeout. Bold text indicates default setting. Security Menu To access this menu, select Security from the menu bar at the top of the screen.
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MPCBL0010 SBC—BIOS Setup Main Advanced PCIPnP Boot Security Chipset Exit NorthBridge Configuration Spread Spectrum Clocking Mode Table 56 describes the sub-menus used to select chipset features. Table 56. Chipset Menu Feature Description Northbridge Configuration Select to display sub-menu Set Northbridge options. Spread Spectrum Clocking Mode Enabled Disabled Enables / Disables Spread Spectrum Clocking for EMI control. Note: 7.7.1 Options Bold text indicates default setting.
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BIOS Setup—MPCBL0010 SBC 7.7.2 Spread Spectrum Clocking Mode Sub-Menu To access this menu, select Chipset from the menu bar and then Spread Spectrum Clocking Mode. Main Advanced PCIPnP Boot Security Chipset Exit NorthBridge Configuration Spread Spectrum Clocking Mode Table 58 describes the Spread Spectrum Clocking Mode options. Table 58. Spread Spectrum Clocking Mode Configuration Feature Spread Spectrum Clocking Mode Note: 7.
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MPCBL0010 SBC—BIOS Setup Table 59. Exit Menu (Continued) Feature Options Description Load FailSafe Defaults Load failsafe default values.
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Error Messages—MPCBL0010 SBC 8.0 Error Messages 8.1 BIOS Error Messages Table 60 lists BIOS error messages and gives an explanation of the message. Table 60. BIOS Error Messages Error Message Explanation Timer Error This timer resides in ICH. Error message indicates an error while programming the count register of the timer. This may indicate a problem with the timer in ICH. CMOS Battery Low BIOS will report this error message when status bit (RTC_REGD.Bit7) in ICH is low.
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MPCBL0010 SBC—Error Messages Table 61. Bootblock Initialization Code Checkpoints Checkpoint Before D1 D1 Table 62. Description Early chipset initialization is done. Early super I/O initialization is done, including RTC and keyboard controller. NMI is disabled. Perform keyboard controller BAT test. Check if waking up from power management suspend state. Save power-on CPUID value in scratch CMOS. D0 Go to flat mode with 4 GByte limit and GA20 enabled. Verify the bootblock checksum.
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Error Messages—MPCBL0010 SBC Table 62. POST Code Checkpoints (Continued) Checkpoint October 2006 Order Number: 304120 Description C7 Early CPU Init Exit. 0A Initializes the 8042-compatible Keyboard Controller. 0B Detects the presence of PS/2 mouse. 0C Detects the presence of Keyboard in KBC port. 0E Testing and initialization of different Input Devices. Also, update the Kernel Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1.
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MPCBL0010 SBC—Error Messages Table 62. POST Code Checkpoints (Continued) Checkpoint A1 Clean-up work needed before booting to OS. A2 Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module. Disables the system configuration display if needed. A4 Initialize runtime language module. A7 Displays the system configuration screen if enabled.
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Addressing—MPCBL0010 SBC 9.0 Addressing 9.1 PCI Configuration Map Table 65 lists the PCI devices and the bus on which they reside. Table 65.
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MPCBL0010 SBC—Addressing Table 65. PCI Configuration Map (Continued) ID SEL# AD17 Funct # BUS # DEV # 0 31 8086h 25A3h 2 i6300ESB ICH – Serial-ATA Controller 0 31 8086h 25A4h 3 i6300ESB ICH – SMBus Controller 1 1 8086h 1229h 0 i82551er i6700PXH – PCI-Express to PCI Bridge (P2P-A) V. ID D.
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Addressing—MPCBL0010 SBC # lspci -t -[00]-+-00.0 +-00.1 +-02.0-[02-04]--+-00.0-[04]-| \-00.2-[03]--+-01.0 (i82546GB, base ch 1) | +-01.1 (i82546GB, base ch 2) | +-02.0 (i82546GB, fabric port 0) | \-02.1 (i82546GB, fabric port 1) +-04.0-[0f-17]-(AMC B2) +-06.0-[06-0e]-(AMC B1) +-1c.0-[05]-+-1d.0 +-1d.1 +-1d.4 +-1d.5 +-1d.7 +-1e.0-[01]----01.0 (i82551 Debug LAN) +-1f.0 +-1f.1 \-1f.3 9.2 FPGA Registers This section describes the Field Programmable Gate Array (FPGA) register settings.
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MPCBL0010 SBC—Addressing Table 67. FPGA Register Overview 80h POST Code low byte 81h POST Code high byte A00h FPGA Version A01h Debug LED Control A02h Firmware Update Manager (manufacturing use only) A03h Reserved for IPMI Controller A04h Development Features A05-A07h Table 68.
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Addressing—MPCBL0010 SBC Note: POST codes are not always 16-bit and the high byte in register 81h could be unrelated to the content of register 80h. Also, only a 16-bit Write to I/O 80h will write to I/O 81h. An 8-bit Write to I/O 81h is ignored. Table 70. FPGA Version 0A00h Address Action D7 D6 D5 Read 0xA00 Write D4 D3 D2 D1 D0 Version Reserved NU Reset Version Version: Programmable logic version. Table 71.
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MPCBL0010 SBC—Addressing Table 72. FWUM 0A02h Address 0xA02 Action D7 D6 D5 D4 D3 D2 D1 D0 Read NU NU Status DoProg Roll-back UART Mode Reset Write NU NU NU DoProg Roll-back UART Mode Reset Reset NU NU NU 0 0 0 1 0 Reset: FWUM reset -- the power-up state of this bit will be 0 under normal operating conditions Mode: FWUM mode pin UART: Set this bit to connect UART1 to the FWUM for programing.
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Addressing—MPCBL0010 SBC SSC1: Special Serial Connection bit 1 SSC1/SSC0: 01: Float the FW_RXD pin -- use this to program the FWUM 10: Connect FW_RXD and FW_TXD to an RJ-45 RS-232 port 00: Connect B1 to ICH UART1 PCB: PCB version. These bits define special connections between serial devices that are meaningless under normal operation. They are for development and/or manufacturing facilities. Leave these bits in their default state for normal operation. Table 74.
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MPCBL0010 SBC—Addressing Table 75. Address 0xA09 Telecom Clock Register 1 0A09h Action D7 D6 D5 D4 D3 D2 D1 D0 Read RSV1 RSV0 SELCLK3B SELCLK3A REFSEL 8K_16M SEL_REFFRQ SEL_RDNCLK Write NU NU SELCLK3B SELCLK3A NU 8K_16M SEL_REFFRQ SEL_RDNCLK Reset X X 0 0 X 0 0 0 SELCLK3B: Select the clock to send to the backplane CLK3B: 0: from the first AdvancedMC (AMC B1, CLKC) 1: from the second AdvancedMC (AMC B2, CLKC).
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Addressing—MPCBL0010 SBC DRVCLKA1: Drives transmission clock CLKA for AdvancedMC B2. This bit is forced to 0 when AdvancedMC B2 is absent or unpowered. DRVCLKA0: Drives transmission clock CLKA for AdvancedMC B1. This bit is forced to 0 when AdvancedMC B1 is absent or unpowered. Table 77. Telecom Clock Register 3 0A0Bh Address Action Read 0xA0B D7 D6 DRVCLK3B D5 DRVCLK3A D4 D3 TXREF1_SEL[2..0] D2 D1 D0 TXREF0_SEL[2..0] Write DRVCLK3B DRVCLK3A TXREF1_SEL[2..0] TXREF0_SEL[2..
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MPCBL0010 SBC—Addressing Note: Use this bit for testing only. In normal operation, leave this bit set to 0. Otherwise, the MPCBL0010 SBC will not be compliant with the AdvancedTCA* specification. RESET: Hardware reset of the PLL Table 80.
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Addressing—MPCBL0010 SBC Table 82. Telecom Clock Register 7 0A0Fh Address 0xA0F Action D7 D6 D5 D4 D3 D2 Read NU NU NU NU Interrupt Number Write NU NU NU NU Interrupt Number Reset X X X X 0101b D1 D0 The content of this register is the number of the legacy ISA interrupt used for events. (See telecom clock register 6). It is initialized at boot time by the BIOS. The interrupt is acknowledged by a Read of telecom clock register 6.
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MPCBL0010 SBC—Addressing Table 83. Table 84.
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Addressing—MPCBL0010 SBC UART: UART override; when set, the serial port to the IPMC will take-over the SBC serial port. when cleared, the IPMC will receive the data (RX) for monitoring purposes but will not be able to transmit LTYPE: LED type. when cleared, whenever possible, amber LEDs are used instead of red. when set, red is used instead of amber. Applicable LEDs: Postcode/HardDisk/Debug LED. PwrBtn: ICH Power Button Control. This bit can be set, but it cannot be cleared.
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MPCBL0010 SBC—Addressing Table 85. SBC Status 01h Address 01h Table 86. 02h D6 D5 D4 D3 D2 D1 D0 Read Vcore 1.2V 1.5V 1.8V 2.5V 3.3V 5V 12V Write NU NU NU NU NU NU NU NU PowerUp NU NU NU NU NU NU NU NU Action D7 D6 D5 D4 D3 D2 D1 D0 Read Last access to I/O 80 in the BIOS address space Write NU NU NU NU NU NU NU NU PowerUp NU NU NU NU NU NU NU NU POST Code High 03h Address 03h Table 88. D7 POST Code Low 02h Address Table 87.
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Addressing—MPCBL0010 SBC LED3: Standard ATCA3 LED control: Heart beat LED, color is amber ULED1: User LED 1, color from LED color control register ULED2: User LED 2, color from LED color control register OLED1: Override LED1. In this implementation, LED1 is controlled by the FWUM. Setting this bit will override the FWUM LED control signal and activate bit LED1 Table 90.
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MPCBL0010 SBC—Addressing Even though authorization is given by the IPMC to drive the clocks to the AdvancedMC module, no actual clocks are driven if the module is not present, unpowered, or illpowered. These bits can be set prior to turning on the AdvancedMC module’s power. A readback returns the state of the bit, but does not reflect the actual clock. In the case of bad power (12VFault=1 for example), the clock is not driven even if the authorization bit is set.
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Addressing—MPCBL0010 SBC Even though authorization is given by the IPMC to drive the clocks to the AdvancedMC module, no actual clocks are driven if the module is not present, unpowered, or illpowered. These bits can be set prior to turning on the AdvancedMC module’s power. A readback will return the state of the bit, but does not reflect the actual clock. In the case of bad power (12VFault = 1, for example), the clock is not driven even if the authorization bit is set.
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MPCBL0010 SBC—Addressing Table 97. ADC1 and ADC2 Grab Data 21-22h Address 21-22h Action D7 D6 D5 D4 D3 D2 D1 D0 Read ADC1 or ADC2 data Write NU NU NU NU NU NU NU NU PowerUp NU NU NU NU NU NU NU NU Address 21h returns ADC1; address 22h returns ADC2 ADC1 measures the current on the main 48V input power ADC1 = (256/4.096)(50K/499)RsIin, Where Rs is the sense resistor set to 0.0033ohm Or, to get the current from the reading: Iin = (4.096/256) )(499/50K)ADC/0.0033 = 0.
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Addressing—MPCBL0010 SBC Table 99. Fabric Control 2 25h Address 25h Action D7 D6 D5 D4 D3 D2 D1 D0 Read NU NU NU ReqClk3B ReqClk3A NU NU NU Write NU NU NU NU NU NU NU NU PowerUp NU NU NU NU NU NU NU NU ReqClk3A: A copy of bit DRVCLK3A of register TelClock3: when this bit is set, the application that configures the TelClock module requests to drive CLK3A in the backplane. ReqClk3B: A copy of bit DRVCLK3B of register TelClock3.
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MPCBL0010 SBC—Addressing SWEv: Switch Event: this bit turns to 1 when the reset switch is pressed and stays at ‘1’ until a 1 is written at this bit position. This bit is used to capture a short pulse on the switch. PCIR: Direct reading of the PCI reset: 1 = PCI reset asserted; 0 = no PCI reset PCIEv: PCI Reset Event: this bit turns to 1 when a PCI reset occurs and stays in this state until a 1 is written at this bit position. This bit is used to capture a short pulse on PCI_RESET.
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Addressing—MPCBL0010 SBC Table 104. Crosspoint Switch Ports Register Chip Port 0 1 Table 105.
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MPCBL0010 SBC—Addressing Table 108.
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Hardware Management Overview—MPCBL0010 SBC 10.0 Hardware Management Overview 10.1 Intelligent Platform Management Controller (IPMC) The MPCBL0010 SBC uses the Renesas* H8S/2168 for the Intelligent Platform Management Controller (IPMC). The IPMC management subsystem provides monitoring, event logging, and recovery control. The IPMC serves as the gateway for management applications to access the platform hardware.
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MPCBL0010 SBC—Hardware Management Overview Figure 22. IPMC Block Diagram ( ,1 3 + %% + I2C , SMBUS2 ! -.
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Hardware Management Overview—MPCBL0010 SBC The FWUM can handle two firmware codes that are stored in two external SEPROMs. If a failure occurs during a firmware upgrade, the FWUM automatically rolls back to the redundant IPMC firmware image. 10.2 Sensor Data Record (SDR) Sensor Data Records contain information about the type and number of sensors in the baseboard, sensor threshold support, event generation capabilities, and the types of sensor readings handled by system management firmware.
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MPCBL0010 SBC—Hardware Management Overview Table 109.
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Hardware Management Overview—MPCBL0010 SBC Table 109. Hardware Sensors (Sheet 3 of 4) Sensor Number Sensor Type Sensor Name (Signal Monitored) Monitored Via Scanning Enabled in Power-Off State (M1) Health LED (Green to Red) 0x2A Voltage Vcc +2.
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MPCBL0010 SBC—Hardware Management Overview Table 109.
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Hardware Management Overview—MPCBL0010 SBC Table 111. OEM Event/Reading Type OEM Name OEM Firmware Information 1 10.3 OEM Number 70h Description Internal diagnostic data. OEM Firmware Information 2 75h Internal diagnostic data. OEM Power Good 77h Discrete sensor indicates power good status. System Event Log (SEL) MPCBL0010 SBC IPMC events are logged and stored in non-volatile memory on the AdvancedTCA shelf manager. There is no local SEL on the MPCBL0010 SBC.
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MPCBL0010 SBC—Hardware Management Overview Table 112. SEL Events Supported (Sheet 2 of 5) Sensor Type System Firmware Progress Sensor Type Code 0Fh Sensor Specific Offset Event Description Unspecified CMOS Settings Wrong, CMOS Checksum Bad, CMOS Date/Time Not Set. Event Data2 = 00h No Usable System Memory Raw R/W test failed.
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Hardware Management Overview—MPCBL0010 SBC Table 112. SEL Events Supported (Sheet 3 of 5) Sensor Type Management Subsystem Health Sensor Type Code Sensor Specific Offset Event Description 01h Controller Access Degraded or Unavailable The storage area used by the IPMC is potentially damaged or some data might have been lost. 00h Sensor Access Degraded The FRUx sensor population could not be entirely merged in. 28h OEM Firmware Information (1) COh - OEM Reserved For development use.
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MPCBL0010 SBC—Hardware Management Overview Table 112. SEL Events Supported (Sheet 4 of 5) Sensor Type OEM Extended Data 2-3 Sensor OEM POST Value Sensor OEM FWUM Status Sensor Type Code C5h C6h Sensor Specific Offset Event Description Generic Discreet Reading Type OEM Extended Data 2-3. When name is "FIA" (FRU Initialization Agent). Sensor used to give the last error that occurred in the FRU InitAgent (FIA).
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Hardware Management Overview—MPCBL0010 SBC Table 112. SEL Events Supported (Sheet 5 of 5) Sensor Type Sensor Type Code 08h Power Supply OEM Event/ Reading 0x77 OEM Power Good reading type AdvancedTCA FRU Hot Swap IPMB Link Sensor Sensor Specific Offset Event Description 00h VCC Good 12V 01h VCC Todd 5V 02h VCC Good 3.3V 03h VCC Good 2.5V 04h VCC Good 1.8V 05h VCC Core 1.5V 06h VCC Good 1.
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MPCBL0010 SBC—Hardware Management Overview 10.4 IPMB Link Sensor The MPCBL0010 SBC provides two IPMB links to increase communication reliability to the shelf manager and other IPM devices on the IPMB bus. These IPMB links work together for increased throughput where both buses are actively used for communication at any point. A request might be received over IPMB Bus A, and the response sent over IPMB Bus B. Any requests that time out are retried on the redundant IPMB bus.
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Hardware Management Overview—MPCBL0010 SBC 10.6 Customizable FRU Area The LinuxCustFru utility is a Linux utility that runs directly on the MPCBL0010 SBC and is available on the Intel web site. This utility can be used to read data from a file and write it to the existing Field Replaceable Unit (FRU) information storage area on the MPCBL0010 SBC, or it can be used to purge any existing customer area in the FRU. The MPCBL0010 SBC provides 512 bytes of space for users to store custom FRU information.
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MPCBL0010 SBC—Hardware Management Overview The example FRU input file below implements the Customer Information Area with two Type-C1 OEM MRA records (in FruCreate format). These two records contain 313 bytes of customer data. The headings _SEE_COMMON and _SEE_MULTIREC are required delimiters in the file. The common area is the FRU Common Header and the Multirec heading delineates the beginning of the MRA data. The first byte of data is the Common Header Format version, which is version 1.
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Hardware Management Overview—MPCBL0010 SBC 51 31 00 // Manufacturer ID - 255 byte record length includes Manufacture ID 00 01 02 03 04 05 06 07// 252 bytes of data 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B
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MPCBL0010 SBC—Hardware Management Overview E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA c1 C1 // Record Type ID == 0xC1 == customer area OEM record 82 // Version Information 40 // Record Length 60 // Record Checksum (zero checksum) 1D // Header Checksum (zero checksum) 5A 31 00 // Manufacturer ID - 64 byte record length includes // Manufacture ID 40 41 42 43 44 45 46 47// 61 bytes of data 30 31 32 33 34 35 36 37 38 39 30 31 32 33 34 35 5A 59 58 57 56 55 54 53 52 51 50 4F 4E 4D 4C 4
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Hardware Management Overview—MPCBL0010 SBC 10.8.1 Command Name NetFunction Command Reset BIOS Flash Type 3A 01h SetBoardDeviceChannelPortSelection 3A 10h GetBoardDeviceChannelPortSelection 3A 11h GetBoardDevicePossibleSelection 3A 13h Set Control State 3E 20h Get Control State 3E 21h Reset BIOS Flash Type This command resets the processor and changes the BIOS bank select signal so the CPU boots using the redundant BIOS bank. Table 114. 10.8.
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MPCBL0010 SBC—Hardware Management Overview Figure 23. AdvancedMC Direct Connect Switch Block Diagram AMC B1 Port 0 AMC B2 Port 1 Port 0 Port 1 Fabric 82546GB LAN A LAN B Fabric Channel 1 Port Port Port Port 0 1 2 3 Fabric Channel 2 Port 0 Port 1 Port 2 Port 3 Disabled 10.8.2.1 SetBoardDeviceChannelPortSelection This command selects the AdvancedTCA channel routing for the installed devices. Table 116.
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Hardware Management Overview—MPCBL0010 SBC 10.8.2.2 GetBoardDeviceChannelPortSelection This command returns the current device AdvancedTCA channel routing selection. Table 117.
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MPCBL0010 SBC—Hardware Management Overview Table 118. GetBoardDevicePossibleSelection (Continued) 1 Completion Code 2-4 Intel IANA number (0x000157) LSB first, MSB last 5-8 Device channel/port selection. Many connections can be set per device.
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Hardware Management Overview—MPCBL0010 SBC Table 121. 10.9 Controls Identifier Control Description Control Number FWH Hub (for BIOS bank information)0 0 FWH 0 Write Protect 1 FWH 1 Write Protect 2 FWH 0 Top Block Lock 3 FWH 1 Top Block Lock4 4 Hot Swap Process The MPCBL0010 SBC can be hot-swapped in and out of a chassis as defined in the AdvancedTCA specification. The onboard IPMC manages the SBC’s power-up and power-down transitions. The steps below illustrates this process: 1.
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MPCBL0010 SBC—Hardware Management Overview 10.9.1 Hot Swap LED The MPCBL0010 SBC supports one blue Hot Swap LED, mounted on the front panel. This LED indicates when it is safe to remove the SBC from the chassis. The on-board IPMC drives this LED to indicate the hot swap state. When the lower ejector handle is press inward, the hot swap switch embedded in the PCB l asserts a HOT_SWAP_PB# signal to the IPMC, and the IPMC moves from the M4 state to the M5 state.
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Hardware Management Overview—MPCBL0010 SBC The MPCBL0010 SBC also has a second "dead time" (45 seconds) used to avoid PCI Express hot plug signaling during the operating system load. This delay is applied from the time the SBC goes to M4 state. There is no hot plug "attention button" during that delay. The IPMC asserts the "attention button" only after the delay to notify the operating system that a new device is ready to power. 10.10.
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MPCBL0010 SBC—Hardware Management Overview Table 123.
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Hardware Management Overview—MPCBL0010 SBC 10.11.1 Processor Events The processor asserts IERR as the result of an internal error. A thermal trip error indicates the processor junction temperature has reached a level where permanent silicon damage may occur. Upon THERMTRIP assertion, the IPMC powers down the boards. This event is logged in the SEL. 10.11.2 DIMM Memory Events The MCH instructs the ICH to report memory parity errors via SMI#.
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MPCBL0010 SBC—Hardware Management Overview initialized. The IPMC firmware defaults to no ACPI until this command is received with proper data in the request to indicate the operating system is either ACPI-enabled or disabled. This command is only executable over the SMS channel. 10.11.6 IPMB Link Sensor The MPCBL0010 SBC provides two IPMB links to increase communication reliability to the shelf manager and other IPMI devices on the IPMB bus.
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Hardware Management Overview—MPCBL0010 SBC 10.12.1 Warm Reset A warm reset occurs when the processor boots after a soft reset request. To qualify as a warm boot, the reset counter located at 40h:D0h must be non-zero (by default, the reset counter and reset flag are initialized to 10 and 1234h by the BIOS after a cold boot). Execution starts at the reset vector. The BIOS initializes and configures all devices except for memory. Memory contents remain intact except for the first 8 MB.
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MPCBL0010 SBC—Hardware Management Overview FRU information in the MPCBL0010 SBC includes data describing the MPCBL0010 SBC board as specified in the PICMG 3.0 requirements. Additional multi-records are added for the BIOS to write CPU information, and the BIOS version number to FRU data correctly. This information is retrieved by the shelf manager (AdvancedTCA ShMC), enabling reporting of board-specific information through an out-of-band mechanism.
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Hardware Management Overview—MPCBL0010 SBC Upon successful verification of the operational code checksum, the firmware jumps to the operational code. When the firmware enters firmware (FW) update mode, the operational code uses a special branch, Software Interrupt, to jump to the FW update code in the boot block. Once in FW update mode, the update code is copied into RAM, then the firmware jumps to the code in RAM to execute.
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MPCBL0010 SBC—Hardware Management Overview Intel NetStructure® MPCBL0010 Single Board Computer Technical Product Specification 144 October 2006 Order Number: 304120
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Serial Over LAN (SOL)—MPCBL0010 SBC 11.0 Serial Over LAN (SOL) Serial over LAN (SOL) is a packet format and protocol defined in the IPMI v2.0 specification for transmitting serial port data over Ethernet using IPMI over LAN (RMCP+) messages. This two-way redirection of a blade's serial port data over Ethernet is independent of the operating system or any applications executing on it.
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MPCBL0010 SBC—Serial Over LAN (SOL) Figure 27 is a block diagram of the SOL implementation on the blade: Figure 27. SOL Block Diagram CPU ATCA Blade PCI Express MCH Ethernet traffic to /from System 82571EB Base Ethernet Ports Packet Filtering LAN Ethernet Ctrlr Ethernet traffic to /from IPMC ICH To Front Panel RJ-45 or RTM COM1 KCS COM1 KCS SMBus IPMC IPMB-0 This architecture requires the following three components to perform Serial over LAN operations. 1.
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Serial Over LAN (SOL)—MPCBL0010 SBC of serial data to and from network packets, and the transmission and reception of SOL network packets through the Ethernet controller sideband interface port. 11.2.2 Architectural Components 11.2.2.1 IPMC As shown in the block diagram in Figure 27, the IPMI controller on the blade provides a UART interface to the blade’s serial port (COM1).
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MPCBL0010 SBC—Serial Over LAN (SOL) To start SOL communication, the user invokes the SOL client utility with the IP address of the blade and a series of authentication parameters (username, password, privilege level, cipher suite, etc). The IPMI v2.0 specification allows for AES encryption algorithms for encryption of payload data sent over the network, including AES-128, which uses 128-bit cipher keys. The SOL client utility initializes the RMCP+ session with the blade and activates SOL.
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Serial Over LAN (SOL)—MPCBL0010 SBC Note: While ipmitool is a supported utility, reference_cfg is provided as an unsupported reference to be modified by customers to suit their specific environments and integration needs. 11.6 Supported Usage Model Customers are expected to use SOL to accomplish the following: • BIOS console redirection • Remote terminal access for OS setup and viewing text console output The ipmitool utility runs on a remote network node and communicates over the LAN interface.
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MPCBL0010 SBC—Serial Over LAN (SOL) 11.7 Reference Script (reference_cfg) 11.7.1 SOL Configuration Reference Script (reference_cfg) The reference script can run with no special setup. The script uses built-in bash commands as well as grep and awk. The environment in which the script runs must have bash installed at /bin/bash (or a symbolic link at that location), and must include grep and awk in the path.
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Serial Over LAN (SOL)—MPCBL0010 SBC IP and MAC addresses supplied to the IPMC are specified on the command-line as shown in Table 125. The IP source is set to “static” and the subnet mask is set for a class C subnet. Gateway IP and MAC addresses should be specified with the command to enable RMCP communication across subnets. If the IP or MAC address options are missing from the command line, these parameters are not be changed on the IPMC. The IP, MAC, gateway, and gateway MAC parameters are optional.
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MPCBL0010 SBC—Serial Over LAN (SOL) Table 125. SOL Configuration Reference Script Command-line Options Option Meaning -n Specifies the MAC address of the subnet’s gateway. -g “Gratuitous ARPs” - Turns on gratuitous ARPs. If this switch is not supplied, then IPMC-generated ARP responses are enabled instead. -v “Version” - displays the version and quits -I “Interface” - specifies the interface used to commuicate to the IPMC. Must be one of kcs, lan, or ipmb.
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Serial Over LAN (SOL)—MPCBL0010 SBC Note: If the default BIOS baud rate is changed to any baud rate other than 9600, then the reference_cfg script needs to be changed to match the same baud rate. Figure 29. BIOS Configuration of SOL Target Blade 11.8.1.2 Operating System Configuration Configure the operating system baud rate to match the BIOS baud rate. 1. For MontaVista: a. Note: Edit the /etc/lilo.conf file. b. Type vi /etc/lilo.conf. c.
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MPCBL0010 SBC—Serial Over LAN (SOL) d. Change the kernel line to read kernel /vmlinuz-2.6.9-34.ELsmp ro root=LABEL=/ console=ttyS0,9600n8 rhgb quiet Here you are adding console=ttyS0,9600n8 rhgb quiet to the end of your kernel line if it does not already exist. e. Figure 30. Type :wq! to save the changes. Configuration for RHEL 3. Ensure that at least one agetty process is running on the serial port. To do this, modify the file /etc/inittab.
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Serial Over LAN (SOL)—MPCBL0010 SBC To configure IP on RedHat RHEL: # vi /etc/sysconfig/network-scripts/ifcfg-ethN 11.8.1.3 sbcutils RPM Installation 1. Install the sbcutils RPM. For complete details on the sbcutils installation, refer to the sbcutilities RPM install procedure on the MPCBL0010 SBC product page a. Copy the RPM to the target blade. Ensure that the RPM copied is for the particular OS installed on the target blade. b. Check the version of sbcutils installed: rpm -q sbcutils c.
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MPCBL0010 SBC—Serial Over LAN (SOL) Execute this command to configure SOL on the target blade: reference_cfg -I kcs -g -i b. Script executed on the Intel CMM Communication will be from the CMM to the target blade through IPMB. Note:This requires an MPCMM0001 or MPCMM0002 chassis and firmware 6.1.0.2779 or later. FTP these two files (/usr/bin/reference_cfg and /usr/lib/sbcutils/ reference_funcs) to the CMM /home/scripts directory. "The CMM default IP address is 10.90.90.91.
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Serial Over LAN (SOL)—MPCBL0010 SBC reference_cfg: Success cmmget -l blade14 -t raw reference_cfg: Success cmmget -l blade14 -t raw reference_cfg: Success cmmget -l blade14 -t raw reference_cfg: Success cmmget -l blade14 -t raw reference_cfg: Success 11.8.2 -d "0x0C 0x21 1 0x03 0x07 0x2A" -d "0x0C 0x21 1 0x04 0x03 0x0A" -d "0x0C 0x21 1 0x05 0x06" -d "0x0C 0x21 1 0x06 0x06" Client Blade Setup The client blade is the SOL blade that activates SOL on the target and receives serial output from the target.
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MPCBL0010 SBC—Serial Over LAN (SOL) 11.8.2.2 Installing ipmitool 1. Download 1.8.7 or newer version of ipmitool from http://ipmitool.sourceforge.net/ 2. Install ipmitool 1.8.7 on the Client Blade. ipmitool provides the SOL client interface. 3. Type: tar zxvf ipmitool-1.8.7.tar.gz 4. Change directory to the ipmitool directory created after tar, cd ipmitool-1.8.7 5. Type: ./configure 6. Type: make install 7. For RedHat* RHEL only: Before using ipmitool, start the IPMI drivers.
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Serial Over LAN (SOL)—MPCBL0010 SBC Use "ipmitool lan print 2" to display the configuration for the second Ethernet channel (This Ethernet port is connected to the Ethernet switch located in Slot #8 on the MPCH0001 chassis) root@DRBlade14:/usr/bin# ipmitool lan print 1 Set in Progress : Set Complete Auth Type Support : NONE MD2 MD5 PASSWORD Auth Type Enable : Callback : : User : : Operator : 11.8.2.5 : Admin : : OEM : IP Address Source : Unspecified IP Address : 10.90.90.
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MPCBL0010 SBC—Serial Over LAN (SOL) Note:After pressing ~ just once, this symbol will not appear on the console screen. This is done at the login prompt. 2. After typing ~ the SOL session will deactivate on the SOL Target Blade.
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Telecom Clock—MPCBL0010 SBC 12.0 Telecom Clock 12.1 Functional Description The MPCBL0010 SBC has a built-in telecom clock synchronization circuit. This circuit uses the Zarlink* ZL30410* Multi-Service Line Card PLL and a PLD that act as a clock multiplexer on inputs and outputs. The clock can be synchronized to the AdvancedTCA* backplane clocks, and the output clocks can be routed to the AdvancedMC* CLKA and CLKB signals. Control and status registers are implemented in the FPGA.
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MPCBL0010 SBC—Telecom Clock 12.2 Interface Description 12.2.1 AdvancedTCA Backplane Interface The redundant reference clock CLK1A /CLK1B (8 kHz), and CLK2A/CLK2B (19.44 MHz), are connected from the AdvancedTCA* backplane. These signals use Multipoint-Low Voltage Differential Signaling (M-LVDS). Since only very short stub lengths are allowed with these signals, M-LVDS to Low Voltage Transistor-Transistor Logic (LV-TTL) level converters have to been placed near to the backplane connectors.
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Telecom Clock—MPCBL0010 SBC • 2.048 MHz • 2.048 MHz • 4.096 MHz • 6.312 MHz • 8.192 MHz, • 8.592 MHz • 11.184 MHz • 19.44 MHz • 34.368 MHz • 44.735 MHz. Note: Only one frequency per AdvancedMC module can be selected. 12.3.3 Recovered Clock Selection Each AdvancedMC module has one clock output. This clock can be forwarded to CLK3A and/or CLK3B on the AdvancedTCA backplane without changing the frequency. The output level converters convert from LVTTL to M-LVDS.
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MPCBL0010 SBC—Telecom Clock Additionally the currently selected redundant reference clock (REFSEL) is available. Since the hitless switchover is executed by hardware automatically, the software only has to read out the current status of the clock selection. 12.4 Telecom Clock API This section describes how to configure the telecom clock using the telecom clock API. The telecom clock API is included with the MontaVista* Linux Support Package (LSP) for the MPCBL0010 SBC.
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Telecom Clock—MPCBL0010 SBC Functions: IOCTL_ENABLE_CLKA0_OUTPUT IOCTL_ENABLE_CLKB0_OUTPUT IOCTL_ENABLE_CLKA1_OUTPUT IOCTL_ENABLE_CLKB1_OUTPUT Possible values: 0x01 = Enables transmission clock 0x00 = Disables transmission clock 12.4.
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MPCBL0010 SBC—Telecom Clock Table 128. Switchover Mode Values Name 12.4.6 Description Value PLL_HOLDOVER Use PLL holdover detection 0x40 LOST_CLOCK Use loss of clock signal 0x00 Select Reference Clock To select the received reference clock from AdvancedMC for AdvancedTCA backplane CLK3B and CLK3A, use the following: Functions: IOCTL_SELECT_RECEIVED_REF_CLK3A IOCTL_SELECT_RECEIVED_REF_CLK3B Table 129. Received Reference Clock Values Name 12.4.
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Telecom Clock—MPCBL0010 SBC 12.4.9 Corner Frequency To select the corner frequency of the PLL loop filter, use the following: Function: IOCTL_FILTER_SELECT Table 132. Corner Frequency Values Name 12.4.10 Description Value FILTER_6HZ Change the corner frequency of the PLL loop filter to 6Hz and limits the phase slope to 41 ns per 1.326 ms. 0x04 FILTER_12HZ Change the corner frequency to 12 Hz without phase slope limitation.
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MPCBL0010 SBC—Telecom Clock Table 134. Hardware Reset Values Name 12.4.13 Description Value RESET_ON Reset asserted 0x00 RESET_OFF Reset deasserted 0x02 Read Alarm States To read alarms state of the telecom clock, use the following: Function: IOCTL_READ_ALARMS Table 135. Alarm State Values Bit 0–3 12.4.14 Description Define Bit Mask None None 4 Unlock detected UNLOCK_MASK 5 Hold over detected. HOLDOVER_MASK Hold over detected.
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Telecom Clock—MPCBL0010 SBC 12.4.15 Read the Current Reference Clock To determine the current reference clock used by the telecom clock, use the following: Function: IOCTL_READ_CURRENT_REF Table 137. Reference Clock Values Current Reference Clock 12.4.16 Value Primary Clock 0 Secondary Clock q sysfs Interface When the Telecom Clock driver is loaded, it creates a sysfs directory under /sys/ devices/platform/telco_clock.
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MPCBL0010 SBC—Telecom Clock > refalign. 12.5 Telecom Clock Registers This section provides descriptions of the Field Programmable Gate Array (FPGA) register settings as they apply to the telecom clock. Note: Unused bits are reserved. To ensure compatibility with other product and upgrades to this product, do not modify unused bits. Table 139. FPGA Register Legend Symbol Description U Unchanged (stay unchanged after reset) X Not Defined NU Not Used See Chapter 9.
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Telecom Clock—MPCBL0010 SBC Table 141.
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MPCBL0010 SBC—Telecom Clock 0 = from first AdvancedMC module (AMC B1, CLKC) 1 = from second AdvancedMC module (AMC B2, CLKC). 8K_16M: This bit is valid only when the transmission clock is selected by setting TXREFx_SEL[2..0]=101 in the TelClock3 register. Setting this bit selects the transmission clock frequency as 16.384 MHz Clearing this bit selects 8.0 kHz. SEL_REFFRQ: Selects the reference frequency (8 k or 19.44 M): 0 = 8 kHz 1=19.
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Telecom Clock—MPCBL0010 SBC Table 144. Telecom Clock Register 3 0A0Bh Address 0xA0B Action D7 D6 D5 D4 D3 D2 D1 D0 Read DRVCLK3B DRVCLK3A TXREF1_SEL[2..0] TXREF0_SEL[2..0] Write DRVCLK3B DRVCLK3A TXREF1_SEL[2..0] TXREF0_SEL[2..0] Reset 0 0 000 000 DRVCLK3B: Enables MLVDS buffer to drive CLK3B to the backplane DRVCLK3A: Enables MLVDS buffer to drive CLK3A to the backplane TXREF1_SEL[2..0]: Transmission reference clock for AdvancedMC module B2 selection (see Table 145 below).
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MPCBL0010 SBC—Telecom Clock Table 147. Telecom Clock Register 5 0A0Dh Address 0xA0D Action D7 D6 D5 D4 D3 D2 Read PCB Version Write NU NU Reset PCB Version D1 D0 PCB: Set to “1” to indicate that the compilation switch was properly set in the source code and that the PLD is compiled for PCB revision 1. VERSION: PLD code version. A value of: PCB&Version = FF: indicates a test PLD to make a clock generator. PCB&Version = FE: indicates a test PLD used during manufacturing tests. Table 148.
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Telecom Clock—MPCBL0010 SBC The interrupt is acknowledged by a read of telecom clock register 6. Always perform a read to this register before enabling the interrupt in the chipset to remove any pending interrupt. A value of ‘2’ hooks the interrupt to an SMI.
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MPCBL0010 SBC—Telecom Clock Table 150.
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Maintenance—MPCBL0010 SBC 13.0 Maintenance 13.1 Supervision Table 151 lists the main components that perform hardware monitoring of voltages and timers. Table 151. Hardware Monitoring Components Component Function Monitors Intelligent Platform Management Controller (IPMC) WDT #1 Commands from the BIOS. If the timer expires (times out), causes a hard reset, power down, or power cycle and IPMI event.
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MPCBL0010 SBC—Thermals 14.0 Thermals The pressure drop versus flow rate curve in Figure 32 represents flow impedance of the slot. This information is provided in accordance with Section 5 of the PICMG 3.0 specification to aid in using the MPCBL0010 SBC SBC in various AdvancedTCA* shelves. Figure 32. Power vs. Flow Rate 0.5 Pressure (inches water) 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.
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Component Technology—MPCBL0010 SBC 15.
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MPCBL0010 SBC—Warranty Information 16.0 Warranty Information 16.
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Warranty Information—MPCBL0010 SBC Intel Business Link (IBL): http://www.intel.com/ibl Telephone No.: 1-800-INTEL4U or 480-554-4904 Office Hours: Monday - Friday 0700-1700 MST Winter / PST Summer 16.3.1 For Europe, Middle East, and Africa (EMEA) Return Material Authorization (RMA) e-mail address EMEA.Returns@Intel.com Direct Return Authorization (DRA) for repair requests e-mail address: EMEA.Returns@Intel.com Intel Business Link (IBL): http://www.intel.com/ibl Telephone No.: 00 44 1793 403063 Fax No.
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MPCBL0010 SBC—Warranty Information POSSIBILITY OF ANY SUCH DAMAGES, INCLUDING, BUT NOT LIMITED TO LOSS OF USE, BUSINESS INTERRUPTIONS, AND LOSS OF PROFITS. NOTWITHSTANDING THE FOREGOING, INTEL'S TOTAL LIABILITY FOR ALL CLAIMS UNDER THIS AGREEMENT SHALL NOT EXCEED THE PRICE PAID FOR THE PRODUCT. THESE LIMITATIONS ON POTENTIAL LIABILITIES WERE AN ESSENTIAL ELEMENT IN SETTING THE PRODUCT PRICE. INTEL NEITHER ASSUMES NOR AUTHORIZES ANYONE TO ASSUME FOR IT ANY OTHER LIABILITIES.
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Customer Support—MPCBL0010 SBC 17.0 Customer Support 17.1 Customer Support This chapter offers technical and sales assistance information for this product. Information on returning an Intel NetStructure® product for service is in the following chapter. 17.2 Technical Support and Return for Service Assistance For all product returns and support issues, please contact your Intel product distributor or Intel Sales Representative for specific information. 17.
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MPCBL0010 SBC—Certifications 18.
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Agency Information—Class B—MPCBL0010 SBC 19.0 Agency Information—Class B 19.1 North America (FCC Class B) Note: In order to ensure compliance to Class B requirements, it is recommended to use shielded cable for installations. FCC Verification Notice This device complies with Part 15 of the FCC Rules.
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MPCBL0010 SBC—Agency Information—Class B 19.4 Korean Class B 19.
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Safety Warnings—MPCBL0010 SBC 20.0 Safety Warnings Caution: Review the following precautions to avoid personal injury and prevent damage to this product or products to which it is connected. To avoid potential hazards, use the product only as specified. Read all safety information provided in the component product user manuals and understand the precautions associated with safety symbols, written warnings, and cautions before accessing parts or locations within the unit.
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MPCBL0010 SBC—Safety Warnings 20.1 Mesures de Sécurité Veuillez suivre les mesures de sécurité suivantes pour éviter tout accident corporel et ne pas endommager ce produit ou tout autre produit lui étant connecté. Pour éviter tout danger, veillez à utiliser le produit conformément aux spécifications mentionnées.
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Safety Warnings—MPCBL0010 SBC 20.2 Sicherheitshinweise Lesen Sie bitte die folgenden Sicherheitshinweise, um Verletzungen und Beschädigungen dieses Produkts oder der angeschlossenen Produkte zu verhindern. Verwenden Sie das Produkt nur gemäß den Anweisungen, um mögliche Gefahren zu vermeiden.
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MPCBL0010 SBC—Safety Warnings 20.3 Norme di Sicurezza Leggere le norme seguenti per prevenire lesioni personali ed evitare di danneggiare questo prodotto o altri a cui è collegato. Per evitare qualsiasi pericolo potenziale, usare il prodotto unicamente come indicato.
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Safety Warnings—MPCBL0010 SBC 20.4 Instrucciones de Seguridad Examine las instrucciones sobre condiciones de seguridad que siguen para evitar cualquier tipo de daños personales, así como para evitar perjudicar el producto o productos a los que esté conectado. Para evitar riesgos potenciales, utilice el producto únicamente en la forma especificada.
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MPCBL0010 SBC—Safety Warnings 20.
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Reference Documents—MPCBL0010 SBC Appendix A Reference Documents The following documents should be available when using this specification. Documents that are not available on web sites can be obtained from your IBL (Intel Business Link) account, or by contacting your Intel Field Sales Engineer (FSE) or Field Application Engineer (FAE). • AdvancedTCA* Specification (http://www.advancedtca.org) • PICMG* Advanced Mezzanine Card AMC.0 Specification D0.97, September, 2004 (http://www.picmg.
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MPCBL0010 SBC—Reference Documents • Low Pin Count (LPC) Interface specification (http://www.intel.com/design/chipsets/ industry/lpc.htm) • Low Voltage Intel® Xeon™ Processor Datasheet (http://www.intel.com/design/ xeon/documentation.htm) • Low Voltage Intel® XeonTM Processor Product Page (http://www.intel.com/ products/server/processors/server/xeon/ index.
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List of Supported Commands (IPMI v1.5 and PICMG 3.0)—MPCBL0010 SBC Appendix B List of Supported Commands (IPMI v1.5 and PICMG 3.0) Table 153. IPMI 1.5 Supported Commands (Sheet 1 of 2) IPM Device Global Commands NetFn1 CMD IPMI 1.5 Spec Func Get Device ID1 App 01h 17.1 Cold Reset App 02h 17.2 Get Self Test Results App 04h 17.4 Broadcast "Get Device ID" App TBD 17.9 Command BMC Watchdog Timer Commands NetFn1 CMD IPMI 1.5 Spec Func Reset Watchdog Timer App 22h 21.
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MPCBL0010 SBC—List of Supported Commands (IPMI v1.5 and PICMG 3.0) Table 153. IPMI 1.5 Supported Commands (Sheet 2 of 2) Get Sensor Hysteresis S/E 25h 29.7 Set Sensor Threshold S/E 26h 29.8 Get Sensor Threshold S/E 27h 29.9 Set Sensor Event Enable S/E 28h 29.10 Get Sensor Event Enable S/E 29h 29.11 Get Sensor Reading S/E 2Dh 29.14 FRU Device Commands Command NetFn CMD IPMI 1.5 Spec Func Get FRU Inventory Area Info Storage 10h 28.1 Read FRU Data Storage 11h 28.
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List of Supported Commands (IPMI v1.5 and PICMG 3.0)—MPCBL0010 SBC Table 154. PICMG 3.