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Intel® PXA255 Processor

Developer’s Manual

March, 2003

Order Number: 278693-001

Summary of content (598 pages)

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Intel® PXA255 Processor Developer’s Manual March, 2003 Order Number: 278693-001
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Contents Contents 1 Introduction...................................................................................................................................1-1 1.1 1.2 2 System Architecture .....................................................................................................................2-1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 3 Intel® XScale™ Microarchitecture Features......................................................................
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Contents 3.4 3.5 3.6 3.7 3.8 3.9 4 System Integration Unit ................................................................................................................ 4-1 4.1 iv 3.3.1 32.768 kHz Oscillator............................................................................................ 3-4 3.3.2 3.6864 MHz Oscillator ..........................................................................................3-4 3.3.3 Core Phase Locked Loop ............................................
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Contents 4.2 4.3 4.4 4.5 4.6 5 DMA Controller .............................................................................................................................5-1 5.1 5.2 5.3 5.4 5.5 6 Interrupt Controller...........................................................................................................4-20 4.2.1 Interrupt Controller Operation .............................................................................4-20 4.2.2 Interrupt Controller Register Definitions......
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Contents 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 7 LCD Controller..............................................................................................................................7-1 7.1 7.2 vi 6.2.1 SDRAM Interface Overview.................................................................................. 6-2 6.2.2 Static Memory Interface / Variable Latency I/O Interface .....................................6-3 6.2.3 16-Bit PC Card / Compact Flash Interface ...................
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Contents 7.3 7.4 7.5 7.6 7.7 8 Synchronous Serial Port Controller ..............................................................................................8-1 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 9 7.2.2 Disabling the Controller ........................................................................................7-5 7.2.3 Resetting the Controller ........................................................................................7-5 Detailed Module Descriptions ..............................
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Contents 9.4 9.5 9.6 9.7 9.8 9.9 10 UARTs ........................................................................................................................................10-1 10.1 10.2 10.3 10.4 10.5 11 Feature List......................................................................................................................10-1 Overview..........................................................................................................................10-2 10.2.
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Contents 11.2 11.3 11.4 12 FICP Operation................................................................................................................11-1 11.2.1 4PPM Modulation ...............................................................................................11-2 11.2.2 Frame Format .....................................................................................................11-3 11.2.3 Address Field.................................................................................
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Contents 12.7 13 AC’97 Controller Unit..................................................................................................................13-1 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 14 Overview..........................................................................................................................13-1 Feature List......................................................................................................................13-1 Signal Description...........
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Contents 14.4 14.5 14.6 14.7 14.8 15 14.3.1 Initialization .........................................................................................................14-3 14.3.2 Disabling and Enabling Audio Replay.................................................................14-4 14.3.3 Disabling and Enabling Audio Record ................................................................14-4 14.3.4 Transmit FIFO Errors .......................................................................................
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Contents 15.5 15.6 16 Network SSP Serial Port ............................................................................................................16-1 16.1 16.2 16.3 16.4 16.5 16.6 17 Overview..........................................................................................................................16-1 Features...........................................................................................................................16-1 Signal Description.........................
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Contents 17.5 17.6 17.4.3 Autoflow Control .................................................................................................17-7 17.4.4 Auto-Baud-Rate Detection..................................................................................17-7 17.4.5 Slow Infrared Asynchronous Interface ................................................................17-8 Register Descriptions.....................................................................................................17-10 17.5.
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Contents 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 6-30 6-31 6-32 6-33 6-34 6-35 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 8-1 8-2 8-3 8-4 9-1 xiv Flash Memory Reset Using State Machine .............................................................................6-42 Flash Memory Reset Logic if Watchdog Reset is Not Necessary ...........................................6-42 MSC0/1/2................................................
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Contents 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 10-1 10-2 10-3 10-4 11-1 11-2 11-3 12-1 12-2 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 14-1 14-2 14-3 15-1 15-2 15-3 15-4 15-5 15-6 16-1 16-2 16-3 16-4 16-5 Start and Stop Conditions..........................................................................................................9-5 START and STOP Conditions ...................................................................................................
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Contents 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 16-14 16-15 16-16 16-17 17-1 17-2 17-3 17-4 Motorola SPI* Frame Protocols for SPO and SPH Programming (single transfers) .................................................................................................................................16-9 National Semiconductor Microwire* Frame Protocol (multiple transfers) ..............................16-10 National Semiconductor Microwire* Frame Protocol (single transfers) ............................
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Contents 3-21 3-22 3-23 3-24 3-25 3-26 3-27 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 4-41 4-42 4-43 CKEN Bit Definitions................................................................................................................3-36 OSCC Bit Definitions ......................................................................................................
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Contents 4-44 4-45 4-46 4-47 4-48 4-49 4-50 4-51 4-52 4-53 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-20 6-19 6-21 6-22 6-23 6-24 6-25 6-26 6-27 xviii OSCR Bit Definitions ...............................................................................................................4-37 OSSR Bit Definitions ........................................................................................................
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Contents 6-28 6-29 6-30 6-31 6-32 6-33 6-34 6-35 6-36 6-37 6-38 6-39 6-40 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 8-1 8-2 8-3 8-4 8-5 8-6 8-7 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 10-1 10-2 Common Memory Space Write Commands ............................................................................6-63 Common Memory Space Read Commands ............................................................................6-63 Attribute Memory Space Write Commands .......
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Contents 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 12-16 12-17 12-18 12-19 12-20 12-21 12-22 12-23 xx RBR Bit Definitions ..................................................................................................................10-6 THR Bit Definitions ..............................................................
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Contents 12-24 12-25 12-26 12-27 12-28 12-29 12-30 12-31 12-32 12-33 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 13-17 13-18 13-19 13-20 13-21 13-22 13-23 13-24 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 15-1 15-2 15-3 15-4 UFNHR Bit Definitions ...........................................................................................................12-43 UFNLR Bit Definitions...................................................................
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15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 15-13 15-14 15-15 15-16 15-17 15-18 15-19 15-20 15-21 15-22 15-23 15-24 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 17-12 17-13 17-14 17-15 17-16 17-17 17-18 17-19 17-20 MMC_STRPCL Bit Definitions ...............................................................................................15-23 MMC_STAT Bit Definitions..................................................................................
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Contents Intel® PXA255 Processor Developer’s Manual xxiii
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Contents Revision History xxiv Date Revision March 2003 -001 Description Initial release Intel® PXA255 Processor Developer’s Manual
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Introduction 1 This document applies to the Intel® PXA255 Processor (PXA255 processor). It is an application specific standard product (ASSP) that provides industry-leading MIPS/mW performance for handheld computing applications. The processor is a highly integrated system on a chip and includes a high-performance low-power Intel® XScale™ microarchitecture with a variety of different system peripherals. The PXA255 processor is a 17x17mm 256-pin PBGA package configuration for high performance.
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Introduction • • • • • • • • • • • • • • 1.2.1 DMA Controller LCD Controller AC97 I2S MultiMediaCard FIR Communication Synchronous Serial Protocol Port I2C General Purpose I/O pins UARTs Real-Time Clock OS Timers Pulse Width Modulation Interrupt Control Memory Controller The Memory Controller provides glueless control signals with programmable timing for a wide assortment of memory-chip types and organizations.
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Introduction 1.2.4 DMA Controller (DMAC) The DMAC provides sixteen prioritized channels to service transfer requests from internal peripherals and up to two data transfer requests from external companion chips. The DMAC is descriptor-based to allow command chaining and looping constructs. The DMAC operates in Flow-Through Mode when performing peripheral-to-memory, memory-toperipheral, and memory-to-memory transfers. The DMAC is compatible with peripherals that use word, half-word, or byte data sizes. 1.
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Introduction 1.2.10 Synchronous Serial Protocol Controller (SSPC) The SSP Port provides a full-duplex synchronous serial interface that operates at bit rates from 7.2 kHz to 1.84 MHz. It supports National Semiconductor’s Microwire*, Texas Instruments’ Synchronous Serial Protocol*, and Motorola’s Serial Peripheral Interface*. The SSPC has FIFOs with DMA access to memory. 1.2.
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Introduction 1.2.13.4 Hardware UART (HWUART) The PXA255 processor has a UART with hardware flow control. The HWUART provides a partial set of modem control pins: nCTS and nRTS. These modem control pins provide full hardware flow control. Other modem control pins can be implemented via GPIOs. The HWUART baud rate is programmable up to 921.6 Kbps. The HWUART’s pins are multiplexed with the PCMCIA control pins. Because of this, these HWUART pins operate at the same voltage as the memory bus.
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Introduction 1-6 Intel® PXA255 Processor Developer’s Manual
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System Architecture 2.1 2 Overview The PXA255 processor is an integrated system-on-a-chip microprocessor for high performance, low power portable handheld and handset devices. It incorporates the Intel® XScale™ microarchitecture with on-the-fly frequency scaling and sophisticated power management to provide industry leading MIPs/mW performance. The PXA255 processor is ARM* Architecture Version 5TE instruction set compliant (excluding floating point instructions) and follows the ARM* programmer’s model.
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System Architecture Figure 2-1. Block Diagram RTC Color or Grayscale LCD Controller OS Timer I2S I2C AC97 DMA Controller and Bridge General Purpose I/O Int. Controller Clocks & Power Man.
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System Architecture Table 2-1. CPU Core Fault Register Bit Definitions System Architecture 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 0 0 0 Reset 0 0 0 [31:6] 0 0 0 0 0 0 0 0 — 0 0 5 4 3 0 0 PSFS Reserved Bit CPU Core Fault 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 Reserved Coprocessor 7 Register 4 0 Reserved. Read undefined.
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System Architecture Table 2-2. ID Bit Definitions [31:24] [23:16] 1 0 0 0 1 0 1 0 0 Core 0 Revision 0 1 0 0 0 Implementation Implementation trademark. Trademark 0x69 – Intel® Corporation. Architecture ARM* Architecture version of the core.
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System Architecture 2.3 I/O Ordering The processor uses queues that accept memory requests from the three internal masters: core, DMA Controller, and LCD Controller. Operations issued by a master are completed in the order they were received. Operations from one master may be interrupted by operations from another master. The processor does not provide a method to regulate the order of operations from different masters.
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System Architecture Each interrupt goes through the Interrupt Controller Mask Register and then the Interrupt Controller Level Register directs the interrupt into either the IRQ or FIQ. If an interrupt is taken, the software may read the Interrupt Controller Pending Register to identify the source. After it identifies the interrupt source, software is responsible for servicing the interrupt and clearing it in the source unit before exiting the service routine. Note: 2.
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System Architecture Table 2-4.
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System Architecture 2.9 Power on Reset and Boot Operation Before the device that uses the processor is powered on, the system must assert nRESET and nTRST. To allow the internal clocks to stabilize, all power supplies must be stable for a specified period before nRESET or nTRST are deasserted. When nRESET is asserted, nRESET_OUT is driven active and can be used to reset other devices in the system. For additional information, see the Intel® PXA255 Processor Design Guide.
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System Architecture Table 2-5. Processor Pin Types Type Function IA Analog Input OA Analog output IAOA Analog bidirectional SUP Supply pin (either VCC or VSS) Table 2-6 describes the PXA255 processor pins. Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 1 of 9) Pin Name Type Signal Descriptions Reset State Sleep State Memory Controller Pins MA[25:0] OCZ Memory address bus. (output) Signals the address requested for memory accesses.
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System Architecture Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 2 of 9) Pin Name Type SDCLK[1] OCZ SDCLK[2] OC nCS[5]/ GPIO[33] nCS[4]/ GPIO[80] nCS[3]/ GPIO[79] nCS[2]/ GPIO[78] nCS[1]/ GPIO[15] Signal Descriptions Reset State Sleep State Driven Low Driven Low Driven Low Driven Low Static chip selects. (output) Chip selects to static memory devices such as ROM and Flash. Individually programmable in the memory configuration registers.
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System Architecture Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 3 of 9) Pin Name nPIOW/ GPIO[51] nPIOR/ GPIO[50] nPCE[2]/ GPIO[53] nPCE[1]/ GPIO[52] nIOIS16/ GPIO[57] nPWAIT/ GPIO[56] PSKTSEL/ GPIO[54] nPREG/ GPIO[55] Type Signal Descriptions Reset State Sleep State ICOCZ PCMCIA I/O write. (output) Performs write transactions to PCMCIA I/O space. Hi-Z - Note [1] Note [5] ICOCZ PCMCIA I/O read. (output) Performs read transactions from PCMCIA I/O space.
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System Architecture Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 4 of 9) Pin Name L_DD[13]/ GPIO[71] L_DD[14]/ GPIO[72] L_DD[15]/ GPIO[73] L FCLK/ GPIO[74] L LCLK/ GPIO[75] L PCLK/ GPIO[76] L BIAS/ GPIO[77] Type ICOCZ ICOCZ Signal Descriptions Reset State LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel. 3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator. LCD display data.
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System Architecture Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 5 of 9) Pin Name BTCTS/ GPIO[44] BTRTS/ GPIO[45] Type Signal Descriptions Reset State Sleep State ICOCZ Bluetooth UART Clear-to-Send. (input) Hi-Z - Note [1] Note [3] ICOCZ Bluetooth UART Data-Terminal-Ready. (output) Hi-Z - Note [1] Note [3] Hi-Z - Note [1] Note [3] Hi-Z - Note [1] Note [3] Standard UART and ICP Pins IRRXD/ GPIO[46] IRTXD/ GPIO[47] ICOCZ IrDA receive signal.
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System Architecture Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 6 of 9) Pin Name Type Signal Descriptions Reset State Sleep State MMCCLK/ GP[6] ICOCZ MMC clock. (output) Clock signal for the MMC Controller. Hi-Z - Note [1] Note [3] MMCCS0/ GP[8] ICOCZ MMC chip select 0. (output) Chip select 0 for the MMC Controller. Hi-Z - Note [1] Note [3] MMCCS1/ GP[9] ICOCZ MMC chip select 1. (output) Chip select 1 for the MMC Controller.
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System Architecture Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 7 of 9) Pin Name SDATA_OUT/ GPIO[30] SYNC/ GPIO[31] nACRESET Type ICOCZ Signal Descriptions AC97 Audio Port data out. (output) Output from the PXA255 processor to Codecs 0 and 1. Reset State Sleep State Hi-Z - Note [1] Note [3] Hi-Z - Note [1] Note [3] AC97 Audio Port reset signal. (output) Driven Low Driven Low I2C clock. (bidirectional) Hi-Z Hi-Z I2S data out.
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System Architecture Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 8 of 9) Pin Name Type Signal Descriptions Reset State Sleep State RTCCLK/ GP[10] ICOCZ Real time clock. (output) 1 Hz output derived from the 32kHz or 3.6864MHz output. Hi-Z - Note [1] Note [3] 3.6MHz/GP[11] ICOCZ 3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator. Hi-Z - Note [1] Note [3] 32kHz/GP[12] ICOCZ 32 kHz clock. (output) Output from the 32 kHz oscillator.
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System Architecture Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 9 of 9) Pin Name Type Signal Descriptions Reset State Sleep State IC JTAG test clock. (input) Clock for all transfers on the JTAG test interface. Input Input TEST IC Test Mode. (input) Reserved. Must be grounded. Input Input TESTCLK IC Test Clock. (input) Reserved. Must be grounded. Input Input TCK Power and Ground Pins VCC SUP Positive supply for internal logic.
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System Architecture Table 2-7. Pin Description Notes (Sheet 2 of 2) Note Description [5] PCMCIA Control Pins: During Sleep Mode: Can be programmed either to drive the value in the Sleep State Register or to be placed in Hi-Z. To select the Hi-Z state, software must set PCFR[FP]. If it is not set, then during the transition to sleep these pins function as described in [3], above. [6] During sleep, this supply may be driven low. This supply must never be high impedance.
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System Architecture Figure 2-2.
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System Architecture Figure 2-3.
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System Architecture 2.13 System Architecture Register Summary Table 2-8.
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System Architecture Table 2-8.
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System Architecture Table 2-8.
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System Architecture Table 2-8.
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System Architecture Table 2-8.
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System Architecture Table 2-8.
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System Architecture Table 2-8.
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System Architecture Table 2-8.
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System Architecture Table 2-8.
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System Architecture Table 2-8.
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System Architecture Table 2-8.
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System Architecture Table 2-8.
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Clocks and Power Manager 3 The Clocks and Power Manager for the PXA255 processor controls the clock frequency to each module and manages transitions between the different power manager (PM) operating modes to optimize both computing performance and power consumption. 3.1 Clock Manager Introduction The Clocks and Power Manager provides fixed clocks for each peripheral unit.
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Clocks and Power Manager 3.2 Power Manager Introduction The Clocks and Power Manager can place the processor in one of three resets. • Hardware Reset (nRESET asserted) is a nonmaskable total reset. It is used at power up or when no system information requires preservation. • Watchdog Reset is asserted through the Watchdog Timer and resets the system except the Clocks and Power Manager. This reset is used as a code monitor.
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Clocks and Power Manager The clocks manager also contains clock gating for power reduction. Figure 3-1 shows a functional representation of the clocking network. “L” is in the core PLL. The PXbus is the internal bus between the Core, the DMA/Bridge, the LCD Controller, and the Memory Controller as shown in Figure 3-1. This bus is clocked at 1/2 the run mode frequency. For optimal performance, the PXbus should be clocked as fast as possible.
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Clocks and Power Manager 3.3.1 32.768 kHz Oscillator The 32.768 kHz oscillator is a low power, low frequency oscillator that clocks the RTC and Power Manager. This oscillator is disabled out of Hardware Reset and the RTC and Power Manager blocks use the 3.6864 MHz oscillator instead. Software writes the Oscillator On bit in the Oscillator Configuration Register to enable the 32.768 kHz.This configures the RTC and Power Manager to use the 32.768 kHz oscillator after it stabilizes. 32.
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Clocks and Power Manager Table 3-1. Core PLL Output Frequencies for 3.6864 MHz Crystal 3.3.4 L M Turbo Mode Frequency (MHz) for Values “N” and Core Clock Configuration Register (CCCR[15:0]) PXbus programming for Values of “N” Frequency (MHz) 1.00 1.50 2.00 3.00 (Run) 27 1 99.5 @1.0 V — 199.1 @1.0 V 298.6 @1.1 V 36 1 132.7 @1.0 V — — 27 2 199.1 @1.0 V 298.6 @1.1 V 36 2 265.4 @1.1 V 45 2 27 4 MEM, LCD Frequency (MHz) SDRAM max Frequency (MHz) 50 99.5 99.5 — 66 132.
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Clocks and Power Manager Table 3-3. 147.46 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal Unit Name 3.3.6 Nominal Frequency Actual Frequency UARTs 14.746 MHz 14.746 MHz AC97 12.288 MHz 12.288 MHz I2S 146.76 MHz 147.46 MHz Clock Gating The Clocks Manager contains the CKEN register. This register contains configuration bits that can disable the clocks to individual units. The configuration bits are used when a module is not being used.
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Clocks and Power Manager Reset, nRESET must be held low for tDHW_NRESET to allow the system to stabilize and the reset state to propagate. Refer to the Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification for details. 3.4.1.2 Behavior During Hardware Reset During Hardware Reset, all internal registers and units are held at their defined reset conditions. While the nRESET pin is asserted, nothing inside the processor is active except the 3.6864 MHz oscillator.
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Clocks and Power Manager 3.4.2.3 Completing a Watchdog Reset Watchdog resets immediately revert to hardware resets when the nRESET pin is asserted. Otherwise, the completion sequence for watchdog reset is: 1. The 3.6864 MHz oscillator and internal PLL clock generators wait for stabilization. The 32.768 kHz oscillator’s configuration and status are not affected by watchdog reset. 2. The nRESET_OUT pin is deasserted after tDHW_OUT.
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Clocks and Power Manager GPIO Reset does not reset the Memory Controller Configuration registers. This creates the possibility that the contents of external memories may be preserved if the external memories are properly configured before GPIO Reset is entered. To preserve SDRAM contents during a GPIO Reset, software must correctly configure the Memory Control and the time spent in GPIO Reset must be shorter than the SDRAM refresh interval.
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Clocks and Power Manager 3.4.5.2 Behavior in Turbo Mode The processor’s behavior in Turbo Mode is identical to its behavior in Run Mode, except that the processor’s clock frequency relative to the memory and peripherals is increased by N, the value in the CCCR (see Section 3.6.1). Turbo mode is intended for use during peak processing, when there are very few accesses to external memory. The higher Core to external memory clock ratio increases the relative delay for each external memory access.
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Clocks and Power Manager 3.4.6.2 Behavior in Idle Mode In Idle Mode the CPU clocks are stopped, but the remainder of the processor operates normally. For example, the LCD controller can continue refreshing the screen with the same frame buffer data in memory. When ICCR[DIM] is cleared, any enabled interrupt wakes up the processor. When ICCR[DIM] is set, only unmasked interrupts cause wake-up. Enabled interrupts are interrupts that are allowed at the unit level.
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Clocks and Power Manager 1. Configure the Memory Controller to ensure SDRAM contents are maintained during the Frequency Change Sequence. The Memory Controller’s refresh timer must be programmed to match the maximum refresh time associated with the slower of two frequencies (current and desired). The SDRAM divide by two must be set to a value that prevents the SDRAM frequency from exceeding the specified frequency.
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Clocks and Power Manager 3.4.7.4 Completing the Frequency Change Sequence The Frequency Change Sequence exits when any Reset is asserted. In Hardware and Watchdog Resets, the Reset entry and exit sequences take precedence over the Frequency Change Sequence and the PLL resumes in its Reset condition. In GPIO Reset, the Reset exit sequence is delayed while the PLL relocks and the frequency is set to the desired frequency of the Frequency Change Sequence.
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Clocks and Power Manager • SDRAM is placed in self refresh before entering 33-MHz idle mode, because SDRAM cannot be refreshed correctly in 33-MHz idle mode. Carefully consider the processor interrupt behavior when the SDRAM in self refresh. To allow the interrupts to occur while SDRAM is in self refresh, set the I and F bits in the CPSR. This allows interrupts to wake the processor from idle mode without jumping to the interrupt handler.
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Clocks and Power Manager 3.4.8.3 Exiting 33-MHz Idle Mode The 33-MHz idle mode exit procedure is the same as the exit procedure for normal idle mode. However, because the I and F bits are set in the CPSR, the processor does not immediately jump to the interrupt vector. Instead processing continues with the instruction following the last executed instruction before 33-MHz idle mode was entered. If execution occurs from SDRAM, steps 1 and 2 must have been previously loaded into the instruction cache.
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Clocks and Power Manager 3.4.9.2 Preparing for Sleep Mode Before Sleep Mode starts, software must take the following steps: 1. The Memory Controller must be configured to ensure SDRAM contents are maintained during Sleep Mode. See Section 6, “Memory Controller” for details. 2. If a graceful shutdown is required for a peripheral, the peripheral must be disabled before Sleep Mode asserts. This includes monitoring DMA transfers to and from peripherals or memories to ensure they are completed.
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Clocks and Power Manager If the external voltage regulator is failing or the main battery is low or missing, some systems must enter sleep mode quickly. When nBATT_FAULT or nVDD_FAULT is asserted, the system is required to shut down immediately. To allow the assertion of nVDD_FAULT or nBATT_FAULT to cause an imprecise data abort, set the Imprecise Data Abort Enable (IDAE) bit in the PMCR.
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Clocks and Power Manager 7. The CPU clock stops and power is removed from the Core. 8. PWR_EN is deasserted. When the Power Manger get the indication from the Memory Controller that it has finished its outstanding transactions and has put the SDRAM into self-refresh, there are eight core clock cycles before the GPIOs latch the PGSR values and four core clock cycles after that, nRESET_OUT asserts low.
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Clocks and Power Manager 2. The PWR_EN signal is asserted and the Power Manager waits for the external power supply to stabilize. If nVDD_FAULT is asserted after the external power supply timer expires, the processor returns to Sleep Mode. 3. If PCFR[OPDE] and OSCC[OON] were set when Sleep Mode started, the 3.6864 MHz oscillator is enabled and stabilizes. Otherwise, the 3.6864 MHz oscillator is already stable and this step is bypassed. 4.
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Clocks and Power Manager 3.4.10 Power Mode Summary Table 3-4 shows the actions that occur when a Power Mode is entered. Table 3-5 shows the actions that occur when a Power Mode is exited. In the tables, an empty cell means that the power mode skips that step. Table 3-6 shows the expected behavior for power supplies in each power mode.
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Clocks and Power Manager 12 Restart CPU clocks, enable interrupts x x Freq Change Idle x x Fault1 Sleep Deassert nRESET_OUT Sleep 11 Run (from Turbo) Description of Action Turbo Step Table 3-5. Power Mode Exit Sequence Table (Sheet 2 of 2) x x x x 1: Fault Sleep Mode starts if IDAE is clear and nBATT_FAULT or nVDD_FAULT is asserted.
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Clocks and Power Manager Table 3-6. Power and Clock Supply Sources and States During Power Modes Power Mode Supply Source Module Turbo Pw Ck Idle Freq Change T R Off changing (R/T) Memory Controller LCD Controller Mem On VCC DMA Controller On Off Off On On On 3.686 MHz Osc Interrupts VCC/ Reg (V/R) 32.768 kHz Osc GP[3:0], PM HV/ Dynamic/ Batt pads, Osc Static (H/B) pads (D/S) General IO On PLL OS timer Power Manager On On General Periphs.
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Clocks and Power Manager 3.5.1 Power Manager Control Register (PMCR) The PMCR is used to select the manner in which Sleep Mode is entered when the nVDD_FAULT or the nBATT_FAULT pin is asserted low. When the IDAE bit is set, an Imprecise Data Abort indication is sent to the CPU. The CPU then performs an abort routine. Software must ensure that the abort routine sets the Sleep Mode configuration in the PWRMODE register (see Section 3.7.2, “Power Mode Register (PWRMODE)”).
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Clocks and Power Manager 3.5.2 Power Manager General Configuration Register (PCFR) The PCFR contains bits used to configure functions in the processor. When the OPDE bit is set, it allows the 3.6864 MHz oscillator to be disabled during Sleep Mode. The OPDE bit is cleared in Hardware, Watchdog, and GPIO Resets. The Float PCMCIA (FP) and Float Static Memory (FS) bits control the state of the PCMCIA control pins and the static memory control pins during Sleep Mode. This is a read/write register.
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Clocks and Power Manager 3.5.3 Power Manager Wake-Up Enable Register (PWER) Table 3-9 shows the location of all wake up source enable bits in the Power Manager Wake-Up Enable Register (PWER). If a GPIO is to be used as a wake up source from Sleep, it must be programmed as an input in the GPDR and either one or both of the corresponding bits in the PRER and PFER must be set.
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Clocks and Power Manager 3.5.4 Power Manager Rising-Edge Detect Enable Register (PRER) The PRER, shown in Table 3-10, determines whether the GPIO pin enabled with the PWER register causes a wake up from sleep mode on that GPIO pin’s rising edge. When PWER[IDAE] is zero and a fault condition is detected on the nVDD_FAULT or nBATT_FAULT pin, PRER is set to 0x0000_0003. This enables rising edges on GP[1:0] to act as wake up sources.
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Clocks and Power Manager 3.5.5 Power Manager Falling-Edge Detect Enable Register (PFER) The PFER, Table 3-11, determines if the GPIO pin enabled with the PWER causes a wake up from sleep mode on that GPIO pin’s falling edge. When PWER[IDAE] is zero and a fault condition is detected on the nVDD_FAULT or nBATT_FAULT pin, PFER is set to 0x0000_0003. This enables falling edges on GP[1:0] to act as wake up sources.
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Clocks and Power Manager 3.5.6 Power Manager GPIO Edge Detect Status Register (PEDR) The PEDR, Table 3-12, indicates which of the GPIO pins enabled through the PWER, PRER, and PFER registers caused a wake up from sleep mode. The bits in PEDR can only be set on a rising or falling edge on a given GPIO pin. If PRER is set, the bits in PEDR can only be set on a rising edge. If PFER is set, the bits in PEDR can only be set on a falling edge. To reset a bit in PEDR to zero, write a 1 to it.
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Clocks and Power Manager 3.5.7 Power Manager Sleep Status Register (PSSR) The PSSR, shown in Table 3-13, contains the following status flags: • Software Sleep Status (SSS) flag is set when the sleep mode configuration in the PWRMODE register is set and sleep mode starts (see Section 3.7.2). • Battery Fault Status (BFS) bit is set after wake up any time the nBATT_FAULT pin is asserted (even when the processor is already in sleep mode).
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Clocks and Power Manager Table 3-13. PSSR Bit Definitions (Sheet 2 of 2) Clocks and Power Manager 5 0 0 0 1 reserved Reset 0 0 0 0 0 Bits 0 0 0 0 0 0 0 0 0 0 0 0 0 Name 0 0 0 0 0 4 3 2 1 0 SSS 6 BFS 7 VFS 8 PH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 reserved Bit PSSR RDH 0x40F0_0004 0 0 0 0 0 Description VDD Fault Status. 2 0 – nVDD_FAULT pin has not been asserted since it was last cleared by a reset or the CPU.
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Clocks and Power Manager 3.5.9 Power Manager Fast Sleep Walk-up Configuration Register (PMFW) The PSPR, shown in Table 3-15, provides a single bit called FWAKE which is used to select between the standard and fast sleep walk-up sequences. The PMFW register is reset by a hardware reset, GPIO reset, watchdog reset, but is not cleared by the sleep walk-up sequence.
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Clocks and Power Manager Table 3-16.
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Clocks and Power Manager Table 3-18.
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Clocks and Power Manager Table 3-19. RCSR Bit Definitions Clocks and Power Manager 7 6 5 4 3 0 0 0 0 0 reserved Reset 0 0 0 0 0 0 0 Bits Name [31:4] — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 HWR 8 WDR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 GPR Bit RCSR SMR 0x40F0_0030 0 0 0 1 Description reserved GPIO Reset. 3 GPR 0 – GPIO reset has not occurred since the last time the CPU or hardware reset cleared this bit.
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Clocks and Power Manager Memory frequency = 3.6864 MHz crystal freq.
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Clocks and Power Manager 3.6.2 Clock Enable Register (CKEN) CKEN, shown in Table 3-21, enables or disables the clocks to most of the peripheral units. For lowest power consumption, the clock to any unit that is not being used must be disabled by writing a zero to the appropriate bit. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 3-21.
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Clocks and Power Manager Table 3-21.
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Clocks and Power Manager 3.6.3 Oscillator Configuration Register (OSCC) The OSCC, shown in Table 3-22, controls the 32.768 kHz oscillator configuration. It contains two bits, the set-only 32.768 KHz OSCC[OON] and the read-only 32.768 kHz OSCC[OOK]. OSCC[OON] enables the external 32.768 kHz oscillator and can only be set by software. When the oscillator is enabled, it takes up to 10 seconds for to stabilize. When the oscillator is stabilized, the processor sets OSCC[OOK].
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Clocks and Power Manager Table 3-23. Coprocessor 14 Clock and Power Management Summary Function Data in Rd Instruction Read CCLKCFG — MRC p14, 0, Rd, c6, c0, 0 Enter turbo mode TURBO = 1 MCR p14, 0, Rd, c6, c0, 0 FCS = 1 (Turbo mode bit may be set or cleared in the same write) MCR p14, 0, Rd, c6, c0, 0 Enter idle mode M=1 MCR p14, 0, Rd, c7, c0, 0 Enter sleep mode M=3 MCR p14, 0, Rd, c7, c0, 0 Enter frequency change sequence 3.7.
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Clocks and Power Manager 3.7.2 Power Mode Register (PWRMODE) The PWRMODE register (CP14, register 7), shown in Table 3-25, is used to enter idle and sleep modes. To select a mode, software writes to PWRMODE[M]. All core-initiated memory requests are completed before the Clocks and Power Manager initiates the desired mode. Table 3-25.
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Clocks and Power Manager 3.8.3 Driving the Crystal Pins from an External Clock Source The information in this section is provided as a guideline. The electrical specifications for the crystal oscillator pins are in Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification. A 3.6864 MHz crystal must be connected between the PXTAL and PEXTAL pins. A 32.768 kHz crystal is normally connected between the TXTAL and TEXTAL pins.
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Clocks and Power Manager . Table 3-27.
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System Integration Unit 4 This chapter describes the System Integration Unit (SIU) for the PXA255 processor. The SIU controls several processor-wide system functions. The units contained in the SIU are: • • • • • 4.
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System Integration Unit When the processor enters sleep mode, the contents of the Power Manager Sleep State registers (PGSR0, PGSR1 and PGSR2) are loaded into the output data registers. If the particular pin is programmed as an output, then the value in the PGSR is driven onto the pin before entering sleep mode.
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System Integration Unit For more information on alternate functions, refer to the Source Unit column in Table 4-1 for the appropriate section of this document. Table 4-1.
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System Integration Unit Table 4-1.
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System Integration Unit Table 4-1.
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System Integration Unit Table 4-1.
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System Integration Unit Table 4-2.
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System Integration Unit Table 4-4.
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System Integration Unit Table 4-6.
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System Integration Unit When a GPIO is configured as an output, the state of the pin can be controlled by writing to either the GPSR or GPCR. An output pin is set high by writing a one to its corresponding bit within the GPSR. To clear an output pin, a one is written to the corresponding bit within the GPCR. GPSR and GPCR are write-only registers. Reads return unpredictable values. Writing a zero to any of the GPSR or GPCR bits has no effect on the state of the pin.
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System Integration Unit Table 4-11.
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System Integration Unit Table 4-14.
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System Integration Unit Table 4-15.
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System Integration Unit Table 4-18.
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System Integration Unit 4.1.3.5 GPIO Edge Detect Status Register (GEDR0, GEDR1, GEDR2) GEDR0, GEDR1, GEDR2, shown in Table 4-21, Table 4-22, and Table 4-23, contain a total of 81 status bits that correspond to the 81 GPIO pins. When an edge detect occurs on a pin that matches the type of edge programmed in the GRER and/or GFER registers, the corresponding status bit is set in GEDR. Once a GEDR bit is set by an edge event, the bit remains set until the user clears it by writing a one to the status bit.
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System Integration Unit Table 4-23.
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System Integration Unit Caution: Configuring a GPIO to map to an alternate function that is not available causes indeterminate results. Table 4-24.
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System Integration Unit Table 4-26. GAFR1_L Bit Definitions Physical Address 0x40E0_005C Bit GAFR1_L System Integration Unit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AF47 AF46 AF45 AF44 AF43 AF42 AF41 AF40 AF39 AF38 AF37 AF36 AF35 AF34 AF33 AF32 Reset 0 0 0 0 0 Bits 0 0 0 0 0 0 0 0 0 0 0 0 0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description GPIO Pin ‘x’ Alternate Function Select Bits (where x=32 through 47).
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System Integration Unit Table 4-28. GAFR2_L Bit Definitions Physical Address 0x40E0_0064 Bit GAFR2_L System Integration Unit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AF79 AF78 AF77 AF76 AF75 AF74 AF73 AF72 AF71 AF70 AF69 AF68 AF67 AF66 AF65 AF64 Reset 0 0 0 0 0 Bits 0 0 0 0 0 0 0 0 0 0 0 0 0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description GPIO Pin ‘x’ Alternate Function Select Bits (where x=64 through 79).
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System Integration Unit • • • • • • GPIO[1] is an input configured to alternate function 1 (ALT_FN_1_IN) GPIO[5:2] are reserved and configured as normal GPIOs inputs GPIO[12:6] are outputs configured to alternate function 1 (ALT_FN_1_OUT) GPIO[13] is an output configured to alternate function 2 (ALT_FN_2_OUT) GPIO[14] is an input configured to alternate function 1 (ALT_FN_1_IN) GPIO[15] is an output configured to alternate function 2 (ALT_FN_2_OUT) This programming sequence is required for programming th
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System Integration Unit — Interrupt Controller FIQ Pending Register (ICFP) – contains the interrupts from all sources that can generate an FIQ interrupt. The Interrupt Controller Level register (ICLR) is programmed to send interrupts to the ICFP to generate an FIQ. • The second level uses registers contained in the source device (the device generating the firstlevel interrupt bit).
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System Integration Unit After a reset, the FIQ and IRQ interrupts are disabled within the CPU, and the states of all of the interrupt controller registers are set to 0x0. The interrupt controller registers must be initialized by software before interrupts are again enabled within the CPU. 4.2.2.1 Interrupt Controller Mask Register (ICMR) The ICMR, shown in Table 4-30, contains one mask bit per pending interrupt bit (22 total).
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System Integration Unit Table 4-31.
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System Integration Unit 4.2.2.4 Interrupt Controller IRQ Pending Register (ICIP) and FIQ Pending Register (ICFP) The ICIP and the ICFP, shown in Table 4-33 and Table 4-34, contain one bit per interrupt (22 total.) These bits indicate an interrupt request has been made by a unit. Inside the interrupt service routine, read the ICIP and ICFP to determine the interrupt source. In general, software then reads status registers within the interrupting device to determine how to service the interrupt.
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System Integration Unit 4.2.2.5 Interrupt Controller Pending Register (ICPR) The ICPR, shown in Table 4-35, is a 32-bit read-only register that shows all active interrupts in the system. These bits are not affected by the state of the mask register (ICMR). Clearing the interrupt status bit at the source, automatically clears the corresponding ICPR flag, provided there are no other interrupt status bits set within the source unit.
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System Integration Unit Table 4-35.
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System Integration Unit Table 4-35.
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System Integration Unit Table 4-36.
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System Integration Unit In addition to the RCNR, the RTC incorporates a 32-bit, RTC Alarm register (RTAR). The RTAR may be programmed with a value that is compared against the RCNR. One 32-kHz cycle after each rising edge of the HZ clock, the counter is incremented and then compared to the RTAR. If the values match, and the enable bit is set, then the RTC Status register (RTSR) alarm match bit (RTSR[AL]) is set.
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System Integration Unit Table 4-37. RTTR Bit Definitions Physical Address 0x4090_000C Reset System Integration Unit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 LCK Bit RTTR 0 reserved ? ? ? ? DEL ? 0 Bits Name <31> LCK <30:26> — <25:16> DEL <15:0> CK_DIV 0 0 0 0 0 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 CK_DIV 0 0 0 0 0 1 1 1 1 1 1 1 1 Description Locking bit for the trim value. 4.3.2.2 0 – RTTR value is allowed to be altered.
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System Integration Unit 4.3.2.3 RTC Counter Register (RCNR) The RCNR, shown in Table 4-39, is a read/write register. The counter may be written by the processor at any time although it is recommended that the operating system prevent inadvertent writes to the RCNR through the use of the MMU protection mechanisms (refer to the Intel® XScale™ Microarchitecture for the Intel® PXA255 Processor User’s Manual for details of MMU operation.
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System Integration Unit Table 4-40. RTSR Bit Definitions 8 7 6 5 4 3 AL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 HZ System Integration Unit ALE Bit RTSR HZE Physical Address 0x4090_0008 ? ? ? ? ? 0 0 0 0 reserved Reset ? ? ? ? ? ? ? Bits Name <31:4> — <3> HZE <2> ALE <1> HZ <0> AL ? ? ? ? ? / ? ? ? ? ? ? ? ? ? ? 2 1 0 Description reserved HZ interrupt enable. 0 – The HZ interrupt is not enabled.
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System Integration Unit 4.3.3.2 RTTR Value Calculations After the true frequency of the oscillator is known, it must be divided by the desired HZ clock frequency and this value split into integer and fractional portions. The integer portion of the value (minus one) is loaded into the Clock Divider Count field of the RTTR. This value is compared against a 16-bit counter clocked by the output of the oscillator multiplexor at approximately 32 kHz.
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System Integration Unit bring the HZ output frequency down to the proper value. Since the trimming procedure is performed every 1023 (210 -1) seconds, the trim must be set to delete 941.16 clocks every 1023 seconds (.92 x 1023 = 941.16). Load the counter with the hexadecimal equivalent of 941, or 0x3AD. The fractional component of this value cannot be trimmed out and constitutes the error in trimming, described below. This trim setting leaves an error of. 16 cycles per 1023 seconds.
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System Integration Unit also routed to the interrupt controller where they can be programmed to cause an interrupt. OSMR3 also serves as a watchdog match register that resets the processor when a match occurs provided the OS Timer Watchdog Match Enable Register (OWER) is set. You must initialize the OSCR and OSMR registers and clear any set status bits before the FIQ and IRQ interrupts are enabled within the CPU. 4.4.1 Watchdog Timer Operation The OSMR3 can also be used as a watchdog compare register.
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System Integration Unit Table 4-41. OSMR[x] Bit Definitions Physical Address 0x40A0_0000 0x40A0_0004 0x40A0_0008 0x40A0_000C Bit OS Timer Match Register 0-3 (OSMR3, OSMR2, OSMR1, OSMR0) System Integration Unit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 OSMV Reset 0 0 0 0 0 0 0 Bits Name <31:0> OSMV 4.4.2.2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description OS Timer Match Value.
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System Integration Unit 4.4.2.3 OS Timer Watchdog Match Enable Register (OWER) The OWER, shown in Table 4-43, contains a single control bit (bit 0) that enables the watchdog function. This bit is set by writing a one to it and can only be cleared by one of the reset functions such as, hardware reset, sleep reset, watchdog reset, and GPIO reset. Table 4-43.
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System Integration Unit Table 4-45. OSSR Bit Definitions 8 7 6 5 4 3 M0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 M1 System Integration Unit M2 Bit OS Timer Status Register (OSSR) M3 Physical Address 0x40A0_0014 ? ? ? ? ? 0 0 0 0 reserved Reset ? ? ? ? ? ? ? Bits Name <31:4> — ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 1 0 Description reserved Match status channel 3.
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System Integration Unit Figure 4-3. PWMn Block Diagram 3.6864 MHz 6-bit down counter Control Block Clock Gate Value of PWM_CTRLn[PRESCALE] Value of PWM_PERVALn[PV] Comparator RESET Bus Interfac PWM_OUTn PSCLK_PWMn 10-bit up counter FLIP-FLOP Comparator SET Value of PWM_DUTYn[DCYCLE] 4.5.1.1 Interdependencies The PWM unit is clocked off the 3.6864 MHz oscillator output.
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System Integration Unit comparator contains PWM_PERVALn[PV] and clears the PWM_OUT signal low when PWM_PERVALn[PV] + 1 and the 10-bit up counter are equal. Both PWM_PERVALn[PV] and PWM_DUTYn[DCYCLE] are 10 bit fields. Note: 4.5.1.2 Take care to ensure that the value of the PWM_PERVALn register remains larger than PWM_DUTYn register. In the case where PWM_PERVALn is less than PWM_DUTYn the output maintains a high state. Reset Sequence A system reset results in no pulse width modulated signal.
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System Integration Unit Table 4-46.
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System Integration Unit Table 4-47.
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System Integration Unit Table 4-48. PWM_PERVALn Bit Definitions Physical Address 0x40B0_0008 0x40C0_0008 Bit PWM Period Control Registers (PWM_PERVAL0, PWM_PERVAL1) System Integration Unit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 reserved Reset 0 0 0 0 0 0 0 Bits Name <31:10> — 0 0 0 0 0 4 3 2 1 0 0 1 0 0 PV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description reserved PWMn Period Control: <9:0> 4.5.
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System Integration Unit 4.6 System Integration Unit Register Summary 4.6.1 GPIO Register Locations Table 4-49 shows the registers associated with the GPIO block and their physical addresses. Table 4-49.
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System Integration Unit Table 4-49. GPIO Register Addresses (Sheet 2 of 2) 4.6.2 0x40E0_0060 GAFR1_U GPIO alternate function select register GPIO[63:48] 0x40E0_0064 GAFR2_L GPIO alternate function select register GPIO[79:64] 0x40E0_0068 GAFR2_U GPIO alternate function select register GPIO[80] Interrupt Controller Register Locations Table 4-50 shows the registers associated with the interrupt controller block and their physical addresses. Table 4-50.
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System Integration Unit Table 4-52. OS Timer Register Addresses (Sheet 2 of 2) 4.6.5 0x40A0_000C OSMR3 OS timer match register 3 0x40A0_0010 OSCR OS timer counter register 0x40A0_0014 OSSR OS timer status register 0x40A0_0018 OWER OS timer watchdog enable register 0x40A0_001C OIER OS timer interrupt enable register Pulse Width Modulator Register Locations Table 4-53 shows the registers associated with the PWM and the physical addresses used to access them. Table 4-53.
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5 DMA Controller This chapter describes the on-chip DMA controller (DMAC) for the PXA255 processor. The DMAC transfers data to and from main memory in response to requests generated by internal and external peripherals. The peripherals do not directly supply addresses and commands to the memory system. The DMAC has 16 DMA channels, 0 through 15, and every DMA request from the peripheral generates at least one memory bus cycle. 5.1 DMA Description The DMAC supports only flow-through transfers.
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DMA Controller 5.1.1 DMAC Channels The DMAC has 16 channels, each controlled by four 32-bit registers. Each channel can be configured to service any internal peripheral or one of the external peripherals for flow-through transfers. Each channel is serviced in increments of the peripheral device’s burst size and is delivered in the granularity appropriate to that device’s port width.
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DMA Controller must remain deasserted for at least four MEMCLKs. The DMAC registers the transition from 0 to 1 to identify a new request. The external companion chip must not assert another DREQ until the previous DMA data transfer starts. Figure 5-2. DREQ timing requirements dreq_assert_min dreq_deassert_min mem_clk DREQ The PREQ[37:0] bits are the active high internal signals from the on-chip peripherals. Unlike DREQ[1:0], they are level sensitive.
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DMA Controller If all channels request data transfers, the Sets are prioritized in following order: • • • • • • • • Set zero Set one Set zero Set two Set zero Set one Set zero Set three The pattern repeats for the next eight channel services. In each set, the channels are given roundrobin priority. Table 5-2.
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DMA Controller state is incremented, wrapping around from state machine state seven back to state machine state zero. If there is no pending request, the state machine stays in the current state machine state until there is a pending request. See Table 5-4 for priority scheme examples. Table 5-4. Priority Schemes Examples Channels Programmed 5.1.4 DMA Channel Priority ch0, ch1 0,1,0,1,0,1,0,1,etc. ch0, ch15 0,0,0,15,0,0,0,15,etc. ch0, ch4, ch8, ch12 0,4,0,8,0,4,0,12,etc.
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DMA Controller 7. The channel waits for the next request or continues with the data transfer until the DCMD[LENGTH] reaches zero. 8. The DDADR[STOP] is set to a 1 and the channel stops. Figure 5-3 summarizes typical No-Descriptor Fetch Mode operation. Figure 5-3.
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DMA Controller a. Word [0] -> DDADRx register and a single flag bit. Points to the next four-word descriptor. b. Word [1] -> DSADRx register for the current transfer. c. Word [2] -> DTADRx register for the current transfer. d. Word [3] -> DCMDx register for the current transfer. 6. The channel waits for the request or starts the data transfer, as determined by the DCMD[FLOW] source and target bits. 7. The channel transmits a number of bytes equal to the smaller of DCMD[SIZE] and DCMD[LENGTH]. 8.
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DMA Controller Figure 5-4. Descriptor Fetch Mode Channel State RESET (Hardware or Sleep) RUN=0 Valid descriptor not running Uninitialized Channel Error RUN=1 DCMD[FLOWSRC] xor DCMD[FLOWTRG] = 1 Wait for request DDADR[STOP] = 0 Descriptor fetch (running) DCMD[FLOWSRC] & DCMD[FLOWTRG] = 0 DCMD[FLOWSRC] xor DCMD[FLOWTRG] = 1 Transferring Data Request Asserted DDADR[STOP] = 1 DDADR[STOP] = 1 DCMD[LENGTH]≠ 0 & DCMD[FLOWSRC] = 0 & DCMD[FLOWTRG] = 0 Stopped 5.1.4.
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DMA Controller • Wait for Request: Channel is waiting for a request before it starts to transfer the data. • Transfer Data: Channel is transferring data. • Channel Error: Channel has an error. It remains in the stopped state until software clears the error condition, re-initializes the channel, and writes a 1 to the DCSR[RUN] bit. See Section 5.3.1 and Section 5.3.2 for details. • Stopped: Channel is stopped. Figure 5-3 and Figure 5-4 show the progression from state to state. 5.1.
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DMA Controller Figure 5-5. Little Endian Transfers Little Endian DMA Transfers D[31] 3 2 1 D[0] 0 from memory DMAC 3 2 1 3 3 1 0 Word Wide Device 2 From 0 2 1 1 2 0 3 To From 2 0 To/From 5.1.8 1 0 3 To Half-Word Wide Device Byte Wide Device Trailing Bytes The DMA normally transfers bytes equal to the transaction size specified by DCMD[SIZE]. As the descriptor nears the end its data, the number of trailing bytes in the DCMD[LENGTH] field may be smaller than the transfer size.
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DMA Controller • Internal Peripheral to Memory Transfers: Most peripherals do not send a request for trailing bytes for on-chip peripheral to memory transfers. Refer to the appropriate section in this document for details of a peripheral’s operation. If the peripheral sends out a request, the DMA transfers the number of bytes equal to the smaller of DCMD[LENGTH] or DCMD[SIZE]. If software must us programmed I/O to handle the trailing bytes, it must follow this sequence of operation: 1.
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DMA Controller 5.2.1.1 Using Flow-Through DMA Read Cycles to Service Internal Peripherals A flow-through DMA read for an internal peripheral begins when the internal peripheral sends a request, via the PREQ bus, to a DMAC channel that is running and configured for a flow-through read. The number of bytes to be transferred is specified with DCMDx[SIZE]. When the request is the highest priority request, the following process begins: 1.
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DMA Controller 5.2.2 Quick Reference for DMA Programming Use Table 5-5 as a quick reference sheet for programming the DMA. Table 5-5. DMA Quick Reference for Internal Peripherals (Sheet 1 of 2) Unit FIFO Address Width (bytes) DCMD.
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DMA Controller Table 5-5. DMA Quick Reference for Internal Peripherals (Sheet 2 of 2) Unit FIFO Address Width (bytes) DCMD.
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DMA Controller 5.2.3.1 Using Flow-Through DMA Read Cycles to Service External Peripherals A flow-through DMA read for an external peripheral begins when the external peripheral sends a request, via the DREQ[1:0] bus, to a DMAC channel that is running and configured for a flowthrough read. DCMDx[SIZE] specifies the number of bytes to be transferred. When the request is the highest priority request, the follow process begins. 1.
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DMA Controller For a flow-through DMA write to an external peripheral, use the following settings for the DMAC register bits: • • • • • • 5.2.4 DSADR[SRCADDR] = companion chip address DTADR[TRGADDR] = external memory address. DCMD[INCSRCADDR] = 0 DCMD[INCTRGADDR] = 1 DCMD[FLOWSRC] = 1 DCMD[FLOWTRG] = 0 Memory-to-Memory Moves Memory-to-memory moves do not involve the DREQ and PREQ request signals. The processor writes to the DCSR[RUN] bit and a channel is configured for a memory-to-memory move.
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DMA Controller 5.3 DMAC Registers The section describes the DMAC registers. 5.3.1 DMA Interrupt Register (DINT) The DINT, shown in Table 5-6, logs the interrupts for each channel. An interrupt is generated if any of these events occur: • • • • Any kind of transaction error on the internal bus that is associated with the relevant channel. The current transfer finishes successfully and the DCMD[ENDIRQEN] bit is set. The current descriptor loads successfully and the DCMD[STARTIRQEN] bit is set.
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DMA Controller Table 5-7.
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DMA Controller Table 5-7.
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DMA Controller 5.3.3 DMA Request to Channel Map Registers (DRCMRx) DRCMRx, shown in Table 5-8, map each DMA request to a channel. Refer to Table 5-13 for details. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 5-8.
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DMA Controller Table 5-9. DDADRx Bit Definitions Bit DMA Descriptor Address Register (DDADRx) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 reserved DESCRIPTOR ADDRESS Reset DMA Controller Uninitialized Bits 31:4 3:1 Name 0 STOP 0x4000_02x0 0 Description DESCRIPTOR Address of next descriptor (read / write). ADDRESS — reserved Stop (read / write). 0 STOP 0 – Run channel.
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DMA Controller Table 5-10. DSADRx Bit Definitions DMA Source Addr Register (DSADRx) 0x4000_02x4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 SOURCE ADDRESS Reset 4 3 2 1 0 reserved Bit DMA Controller Uninitialized Bits Name 31:3 SRCADDR Description Source Address (read / write). Address of the internal peripheral or address of a memory location. Address of a memory location for companion -chip transfer Source Address Bit 2 2 SRCADDR Reserved if DSADR.
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DMA Controller Table 5-11. DTADRx Bit Definitions DMA Target Addr Register (DTADRx) 0x4000_02x8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 TARGET ADDRESS Reset 1 0 reserved Bit DMA Controller Uninitialized Bits Name 31:3 TRGADDR Description Target Address (read / write): Address of the on chip peripheral or the address of a memory location Address of a memory location for companion chip transfer Target Address Bit 2 2 TRGADDR Reserved if DTADR.
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DMA Controller Table 5-12. DCMDx Bit Definitions (Sheet 1 of 2) 0x4000_02xC Bits 0 0 0 0 0 0 0 0 0 0 0 0 Name 8 reserved 0 WIDTH 0 SIZE 0 ENDIAN 0 reserved FLOWTRG 0 ENDIRQEN FLOWSRC 0 reserved STARTIRQEN INCTRGADDR Reset DMA Controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 INCSRCADDR Bit DMA Command Register (DCMDx) 0 7 6 5 4 3 2 1 0 0 0 0 0 0 LENGTH 0 0 0 0 0 0 0 0 Description Source Address Increment Setting.
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DMA Controller Table 5-12. DCMDx Bit Definitions (Sheet 2 of 2) 0x4000_02xC 0 0 0 Bits Name 18 ENDIAN 0 0 0 0 0 0 0 0 8 reserved 0 WIDTH 0 SIZE 0 ENDIAN 0 reserved FLOWTRG 0 ENDIRQEN FLOWSRC 0 reserved STARTIRQEN INCTRGADDR Reset DMA Controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 INCSRCADDR Bit DMA Command Register (DCMDx) 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 LENGTH 0 0 0 0 0 0 0 0 Description Device Endian-ness.
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DMA Controller 5.4 Examples This section contains examples that show how to: • • • • Set up and start a channel Initialize a descriptor list for a channel that is running Add a descriptor to the end of a descriptor list for a channel that is running Initialize a channel that is going to be used by a direct DMA master Example 1. How to set up and start a channel: The following example shows how to set up a channel to transfer LENGTH words from the address DSADR to the I/O address DTADR.
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DMA Controller 3. In memory, create the descriptor to be added and set its stop bit to a 1. 4. In the memory, manipulate the DDADR of the current chain’s last descriptor such that its DDADR points to the descriptor created in Step 3. 5. In the memory, create a new descriptor that has the same DDADR, DSADR, DTADR, and CMD as those of the stopped DMA channel. The new descriptor is the next descriptor for the list. 6.
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DMA Controller When the external device has data to transfer, it makes a DMA request in the standard way. The DMAC wakes up and reads four words from the device’s I_DESC_OFFS address (the DMAC only transfers four words because the first descriptor has an 8-byte count.). The four words from the external device are written in the DSADR, DTADR, and DCMD fields of the next descriptor.
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DMA Controller Table 5-13. DMA Controller Register Summary (Sheet 2 of 5) Address Name Description 0x4000_0110 DRCMR4 Request to Channel Map Register for BTUART receive Request 0x4000_0114 DRCMR5 Request to Channel Map Register for BTUART transmit Request.
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DMA Controller Table 5-13.
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DMA Controller Table 5-13.
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DMA Controller Table 5-13.
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Memory Controller 6 This chapter describes the external memory interface structures and memory-related registers supported by the PXA255 processor. 6.1 Overview The processor external memory bus interface supports Synchronous Dynamic Memory (SDRAM), synchronous and asynchronous burst modes, Page-mode flash, Synchronous Mask ROM (SMROM), Page Mode ROM, SRAM, SRAM-like Variable Latency I/O (VLIO), 16-bit PC Card expansion memory, and Compact Flash.
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Memory Controller Figure 6-1.
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Memory Controller partition pairs: the 0/1 pair and the 2/3 pair. The partitions in a pair must be identical in size and configuration. The two pairs may be different (for example, the 0/1 pair can be 100 MHz SDRAM on a 32-bit data bus, while the 2/3 pair can be 50 MHz SDRAM on a 16-bit data bus).
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Memory Controller asserted on writes to Variable Latency I/O devices, and nWE is asserted on writes to all other static devices, both synchronous and asynchronous. For SRAM and variable latency I/O, DQM[3:0] are byte selects for both reads and writes. When the processor comes out of reset, it starts fetches and executes instructions at address 0x00, which corresponds to memory selected by nCS<0>. The boot ROM must be located at this address.
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Memory Controller Figure 6-2.
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Memory Controller Figure 6-3 shows an alternate memory configuration. This system uses 2M x 16 SMROM devices in static banks 0 and 1, and RAM devices in static bank 2. Figure 6-3.
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Memory Controller 6.4 Memory Accesses If a memory access is followed by an idle bus period, the control signals return to their inactive state. The address and data signals remain at their previous values to avoid unnecessary bus transitions and eliminate the need for multiple pull-up resistors. Table 6-1 lists all the transactions that the processor can generate. No burst can cross an aligned 32byte boundary.
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Memory Controller 6.4.1 Reads and Writes DQM[3:0] are data masking bits. When asserted (high), the corresponding bit masks the associated byte of data on the MD[31:0] bus. When deasserted (low), the corresponding bit does not mask the associated byte of data on the MD[31:0] bus.
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Memory Controller This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 6-2.
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Memory Controller Table 6-2.
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Memory Controller Table 6-2.
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Memory Controller 6.5.2 SDRAM Mode Register Set Configuration Register (MDMRS) The MDMRS, shown in Table 6-3, issues an Mode Register Set (MRS) command to the SDRAM. The value written in this register is placed directly on address lines MA[24:17] during the MRS command. For MA[16:10], values which are fixed or derived from the MDCNFG register are placed on the address bus. When setting the values to be written out on the address lines, base the values on the addressing mode being used.
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Memory Controller Table 6-3. MDMRS Bit Definitions (Sheet 2 of 2) 0 6.5.2.1 0 0 0 0 0 0 6:4 MDCL0 3 MDADD0 2:0 MDBL0 0 0 0 0 1 0 reserved MDCL2 MDBL2 MDMRS2 MDADD2 Reset Memory Controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 reserved Bit MDMRS 0 1 0 0 8 7 MDMRS0 0 0 0 0 0 0 0 0 3 2 MDCL0 MDADD0 0x4800_0040 6 5 MDBL0 0 0 0 1 4 0 1 1 0 0 SDRAM partition pair 0 CAS Latency - derived from MDCNFG:DTC0.
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Memory Controller Table 6-4.
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Memory Controller This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 6-5.
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Memory Controller Table 6-5.
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Memory Controller Table 6-5.
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Memory Controller 6.5.5 SDRAM Memory Options The Dynamic Memory interface supports up to four partitions, organized as two pairs. Both partitions in a pair must have the same SDRAM size, configuration, timing category, and data bus width.
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Memory Controller Table 6-4 shows how the SDRAM row and column addresses are mapped to the internal SDRAM address. The SDRAM row and column addresses are muxed. The SDRAM row is sent during an Active command and is followed by the column address during the read or write command. MA<20> is driven with 0 during column addressing. BA[1:0] is used to tell the SDRAM which bank is being read from and remains stable during column addressing.
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Memory Controller Table 6-7.
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Memory Controller Table 6-7.
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Memory Controller Table 6-8.
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Memory Controller Table 6-8.
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Memory Controller Table 6-9. Pin Mapping to SDRAM Devices with Normal Bank Addressing (Sheet 2 of 3) # Bits Bank x Row x Col x Data Pin mapping to SDRAM devices for Normal Addressing. MA[24:10] represent the address signals driven from the processor.
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Memory Controller Table 6-9. Pin Mapping to SDRAM Devices with Normal Bank Addressing (Sheet 3 of 3) # Bits Bank x Row x Col x Data Pin mapping to SDRAM devices for Normal Addressing. MA[24:10] represent the address signals driven from the processor.
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Memory Controller Table 6-10. Pin Mapping to SDRAM Devices with SA1111 Addressing (Sheet 2 of 3) # Bits Bank x Row x Col x Data Pin mapping to SDRAM devices for SA1111 Addressing Options. MA[24:10] represent the address signals driven from the PXA255 processor.
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Memory Controller Table 6-10. Pin Mapping to SDRAM Devices with SA1111 Addressing (Sheet 3 of 3) # Bits Bank x Row x Col x Data Pin mapping to SDRAM devices for SA1111 Addressing Options. MA[24:10] represent the address signals driven from the PXA255 processor.
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Memory Controller Table 6-11.
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Memory Controller Figure 6-5. Basic SDRAM Timing Parameters 0ns 50ns tRP 100ns tRCD 150ns 200ns CL SDCLK nSDCS MA[24:0] bank row col nSDRAS nSDCAS nWE DATA 0 DQM[3:0] 1 2 3 0000 tRP = 2 clks tRAS = 2 clks tRCD = 2 clks CL = 2 clks Figure 6-6.
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Memory Controller Figure 6-7. SDRAM_read_samebank_diffrow 0ns 50ns 100ns 150ns tRP = 2 clks tRAS = 7 clks tRCD = 2 clks CL = 2 clks tRAS tRCD CL tRP tRCD CL SDCLK nSDCS MA[24:0] row bank col row col nSDRAS nSDCAS nWE DATA 0 DQM[3:0] 1 2 4 3 5 6 7 0000 0000 Figure 6-8.
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Memory Controller Figure 6-9. SDRAM_write 0ns 25ns 50ns 75ns tRP = 2 clks tRCD = 2 clks tRAS = 2 clks CL = 2 clks tRCD CL SDCLK nSDCS MA[24:0] row col nSDRAS nSDCAS nWE DATA DQM[3:0] 0 1 2 3 mask0 mask1 mask2 mask3 Figure 6-10.
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Memory Controller Figure 6-11. SDRAM 4-Beat Write / 4-Write Same Bank, Same Row 0ns 25ns 50ns 75ns 100ns tRP = 2 clks tRCD = 2 clks tRAS = 2 clks CL = 2 clks tRCD CL SDCLK nSDCS MA[24:0] row col col nSDRAS nSDCAS nWE DATA DQM[3:0] 6.6 0 1 2 3 4 5 6 7 mask0 mask1 mask2 mask3 mask4 mask5 mask6 mask7 Synchronous Static Memory Interface The synchronous static memory interface supports SMROM and non-SDRAM-like Flash memories.
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Memory Controller Table 6-13.
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Memory Controller Table 6-13.
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Memory Controller Table 6-13.
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Memory Controller Table 6-13.
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Memory Controller Table 6-15.
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Memory Controller SXCNFG[RL] fields must match any CAS latencies and RAS latencies programmed in this SXMRS register. Software must ensure that fields match the latencies. In some cases, duplicate information must be programmed. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 6-16. SXMRS Bit Definitions 0x4800_0024 Reset 0 reserved SXMRS2 0 0 0 0 0 1 Bits Name 31 — 30:16 SXMRS2 15 — 14:0 6.6.
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Memory Controller Figure 6-12. SMROM Read Timing Diagram Half-Memory Clock Frequency 0ns 50ns 100ns RL = 2 150ns CL = 5 SDCLK SDCKE command NOP ACT NOP READ NOP STOP NOP nCS[0] nSDRAS nSDCAS MA[24:10] row col nWE nOE d0 MD DQM[3:0] d1 d2 0000 RDnWR 6.6.4 Non-SDRAM Timing SXMEM Operation Non-SDRAM Timing Synchronous Flash operation resets to asynchronous mode (page-mode for reads and asynchronous single word writes).
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Memory Controller Table 6-17. Read Configuration Register Programming Values Bits Field Name Value to Program 2:0 BURST LENGTH 5:3 reserved 6 CLOCK CONFIGURATION 7 BURST SEQUENCE 010 8 Word Burst 000 1 Use rising edge of clock 1 Linear burst Order (INTEL BURST ORDER IS NOT SUPPORTED) N/A 8 WAIT CONFIGURATION 9 DATA OUTPUT CONFIGURATION 10 reserved nWAIT from the Flash device is ignored by the processor.
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Memory Controller Table 6-18. Frequency Code Configuration Values Based on Clock Speed (Sheet 2 of 2) MEMCLK Frequency 6.6.4.1 SDCLK0 Frequency 133 66 147 Not supported 166 Not supported Valid Frequency Configurations MDREFR: K0DB2 1 5/6 Corresponding CAS Latencies 6/7 Non-SDRAM Timing Flash Read Timing Diagram Figure 6-12 shows the burst-of-eight read timing diagram. Figure 6-13.
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Memory Controller For divide-by-two mode, the following timing parameters apply: • nADV assert time = 3 MEMCLKs • MA, nCS setup to nADV asserted = 1 MEMCLK • nADV deasserted to nOE asserted = (Code * 2) - 4 MEMCLKs 6.6.4.2 K3 Synchronous StrataFlash Reset The PXA255 processor nRESET_OUT pin must be connected to the K3 #RST pin for Hardware reset, Watchdog reset and sleep mode to work properly. GPIO reset however does not reset the contents of the memory controller configuration register.
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Memory Controller • • • • Non-burst ROM or Flash memory Burst ROM or Flash SRAM SRAM-like variable latency I/O devices The Variable Latency I/O interface differs from SRAM in that it allows the use of the data-ready input signal, RDY, to insert a variable number of memory-cycle wait states. The data bus width for each chip-select region can be programmed as 16- or 32-bit. nCS[3:0] can also be configured for Synchronous Static Memory (refer to Section 6.6).
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Memory Controller Table 6-19. 32-Bit Bus Write Access Data Size MA[1:0] DQM[3:0] 8-bit 00 1110 8-bit 01 1101 8-bit 10 1011 8-bit 11 0111 16-bit 00 1100 16-bit 10 0011 32-bit 00 0000 Table 6-20.
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Memory Controller This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 6-21.
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Memory Controller Table 6-21.
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Memory Controller Table 6-21.
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Memory Controller Table 6-22 provides a comparison of supported Asynchronous Static Memory types. Table 6-22.
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Memory Controller 6.7.3.1 ROM Timing Diagrams and Parameters Figure 6-17, Figure 6-18, and Figure 6-19 show the timings for burst and non-burst ROMs. Figure 6-17.
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Memory Controller Figure 6-18.
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Memory Controller Figure 6-19. 32-Bit Non-burst ROM, SRAM, or Flash Read Timing Diagram - Four Data Beats (MSC0[RDF] = 4, MSC0[RRR] = 1) MEMCLK nCS[0] RDF+2 RDF+1 0 1 RDF+1 MA[25:2] 2 3 00 MA[1:0] RDF+1 RRR*2+1 RDF+1 nADV(nSDCAS) nOE nWE RDnWR MD[31:0] DQM[3:0] 0000 nCS[1] 6.7.4 SRAM Interface Overview The processor provides a 16-bit or 32-bit asynchronous SRAM interface that uses the DQM pins for byte selects on writes. nCS[5:0] select the SRAM bank.
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Memory Controller For writes to SRAM, if all byte enables are turned off (masking out the data, DQM = 1111), then the write enable are 1 (nWE = 1) for this write beat. This can result in a period when nCS is asserted, but neither nOE nor nWE is asserted. This happens with a write of 1 beat to SRAM, but all byte enables are turned off. Figure 6-20 shows the timing for SRAM writes. Figure 6-20.
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Memory Controller 6.7.5 Variable Latency I/O (VLIO) Interface Overview Variable Latency I/O read accesses differ from SRAM read accesses in that the nOE toggles for each beat of a burst. The first nOE assertion occurs two memory cycles after the assertion of the chip select nCS. Also, for Variable Latency I/O writes, nPWE is used instead of nWE so SDRAM refreshes can be executed while performing the VLIO transfers. Variable Latency I/O is selected by programming the MSCx[RTx] bits as 0b100.
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Memory Controller 6.7.5.1 Variable Latency I/O Timing Diagrams and Parameters Figure 6-21 shows the timing for Variable Latency I/O reads and Figure 6-22 shows the timing for Variable Latency I/O writes. Figure 6-21.
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Memory Controller Figure 6-22.
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Memory Controller 6.7.6 FLASH Memory Interface The processor provides an SRAM-like interface for access of Flash memory. The RDF fields in the MSCx registers are the latency for each read access to non-burst Flash, or the first read access to burst Flash. The RDF fields also control the nWE low time during a write cycle to Flash. The RDN field controls subsequent read access times to burst Flash and the nWE low time during a write cycle to non-burst Flash.
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Memory Controller Figure 6-23.
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Memory Controller 6.8 16-Bit PC Card/Compact Flash Interface The following sections provide information on the card interface based on the PC Card Standard Volume 2 - Electrical Specification, Release 2.1, and CF+ and CompactFlash Specification Revision 1.4. Only 8- and 16-bit data transfers are supported. 6.8.
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Memory Controller Table 6-24.
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Memory Controller Table 6-26.
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Memory Controller Table 6-26.
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Memory Controller 6.8.3 16-Bit PC Card Overview The PXA255 processor 16-bit PC Card interface provides control for one 16-bit PC Card card slot with a PSKTSEL pin for support of a second slot. The PXA255 processor interface supports 8- and 16-bit peripherals and handles common memory, I/O, and attribute-memory accesses. The duration of each access is based on the values programmed in the fields in the MCMEMx, MCATTx, and MCIOx registers. Figure 6-26 shows the memory map for the 16-bit PC Card space.
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Memory Controller When writes goes to a card sockets and a byte has been masked via an internal byte enable, the write does not occur on the external bus. For reads, one half-word is always read from the socket, even if only 1 byte is requested. In some cases, based on internal address alignment, one word is read, even if only 1 byte is requested. All DMA modes are supported in the Card interface increment the address. Table 6-28.
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Memory Controller Table 6-34. 8-Bit I/O Space Write Commands (nIOIS16 = 1) nPCE2 nPCE1 MA<0> nPIOR nPIOW MD[15:8] MD[7:0] 1 0 0 1 0 Unimportant Even Byte 1 0 1 1 0 Unimportant Odd Byte Table 6-35. 8-Bit I/O Space Read Commands (nIOIS16 = 1) nPCE2 nPCE1 MA<0> nPIOR nPIOW 6.8.
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Memory Controller Figure 6-27. Expansion Card External Logic for a One-Socket Configuration Intel® - PXA255 Processor Socket 0 MD<15:0> D<15:0> DIR nOE RD/nWR GPIO nPCD0 GPIO nPCD1 nCD<2> PRDY_BSY0 PADDR_EN0 RDY/nBSY nCD<1> PSKTSEL GPIO GPIO MA[25:0] A[25:0] nWE nPWE nREG nPREG nCE<2:1> nOE nIOR nIOW nPCE<2:1> nPOE nPIOR nPIOW 5V to 3.3V or 2.5V nWAIT nPWAIT 5V to 3.3V or 2.5V nIOIS16 nIOIS16 Figure 6-28 shows the glue logic need for a 2-socket system.
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Memory Controller Figure 6-28.
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Memory Controller 6.8.5 Expansion Card Interface Timing Diagrams and Parameters Figure 6-29 shows a 16-bit access to a 16-bit memory or I/O device. When common memory is accessed, the MCMEM0 and MCMEM1 registers are used, depending on whether card socket 0 or 1 is addressed. MCIO0 and MCIO1 are used for I/O accesses and MCATT0 and MCATT1 are used for access to attribute memory. Figure 6-29.
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Memory Controller Figure 6-30. 16-Bit PC Card I/O 16-Bit Access to 8-Bit Device 0ns 100ns 200ns 300ns MEMCLK MA[25:1],nPREG,PSKTSEL MA[0] nPCE2 nPCE1 IOx_SET IOx_SET IOx_HOLD IOx_HOLD nPIOW,nPIOR RDnWR nIOIS16 IOx_ASST_HOLD IOx_ASST_HOLD IOx_ASST_WAIT + wait states IOx_ASST_WAIT + wait states nPWAIT read_data write_data Low Byte High Byte The interface waits the smallest possible amount of time (x_ASST_WAIT) before it checks the value of the nPWAIT signal.
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Memory Controller Figure 6-31. Alternate Bus Master Mode EXTERNAL SYSTEM Processor SDCKE<1> SDCLK<1> nSDCS(0) nSDRAS Memory Controlle nSDCAS nWE External SDRAM Bank 0 MA[25:0] DQM[3:0] MBGNT MBREQ MD[31:0] Companion Chip GPIO Block GPIO<13> (MBGNT) GPIO<14> (MBREQ) Figure 6-32.
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Memory Controller 6.9.1 Alternate Bus Master Mode The processor supports the presence of an alternate master on the SDRAM memory bus. The alternate master is given control of the bus with a hardware handshake that is performed through MBREQ and MBGNT, which are invoked through the alternate functions on GPIO[14] and GPIO[13], respectively. The Memory Controller performs an SDRAM refresh if SDRAM clocks and clock enable are turned on.
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Memory Controller 7. The Memory Controller performs an SDRAM refresh if SDRAM clocks and clock enable are turned on. 8. The Memory Controller sends an MRS command to the SDRAMs if the MDCNFG:SA1111x bit is enabled. This changes the SDRAM burst length back to four. If the refresh counter for the processor requested a refresh cycle during the alternate master’s tenure, a refresh cycle runs first, followed by any other bus transactions that stalled during that period.
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Memory Controller is deasserted or, as part of the sleep entry routine, the alternate master can be disabled. If necessary, the alternate master can hold the bus until its transaction is completed. After the memory controller has completed all outstanding transactions, it places SDRAM into self-refresh and allows the processor to complete the sleep entry sequence. Note: 6.10 The alternate bus master must de-assert MBREQ when nVDD_FAULT or nBATT_FAULT is asserted.
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Memory Controller Table 6-37.
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Memory Controller 6.10.2.2 Boot-Time Configurations The boot time configurations are shown in Figure 6-33 - Figure 6-35. A boot from a single 32-Mbit SMROM with nWORD = 1 is not supported. Three Configuration registers are affected at reset - MSC0:RBW0, MDREFR:E0PIN/K0RUN, and SXCNFG. Figure 6-33.
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Memory Controller Figure 6-34.
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Memory Controller Figure 6-35.
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Memory Controller Table 6-39.
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Memory Controller being configured, the SDRAM banks must be disabled and MDREFR:APD must be deasserted (auto-power-down disabled). a. Write SXCNFG (with enable bits asserted). b. Write to SXMRS to trigger an MRS command to all enabled banks of synchronous static memory. c. SXLCR must only be written when it is required by the SDRAM-like synchronous flash device for command encoding. 3. In systems that contain SDRAM, transition the SDRAM controller through the following state sequence: a.
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Memory Controller 11. Optionally, in systems that contain SDRAM or Synchronous Static memory, enable autopower-down by setting MDREFR[APD]. 6.12 GPIO Reset Procedure On a GPIO Reset, the Memory Controller registers keep the values they had before the reset. No new configuration programming is required. However, SDRAM refreshes do not occur during the reset time. After nRESET_OUT is deasserted, the memory controller will continue refreshing.
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Memory Controller Table 6-40. Memory Controller Register Summary (Sheet 2 of 2) Physical Address 6-80 Symbol Register Name 0x4800_003C MCIO1 Card interface I/O Space Socket 1 Timing Configuration 0x4800_0040 MDMRS 0x4800_0044 BOOT_DEF Read-Only Boot-time register. Contains BOOT_SEL and PKG_SEL values.
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LCD Controller 7 The LCD controller provides an interface from the PXA255 processor to a passive (DSTN) or active (TFT) flat panel display. Monochrome and several color pixel formats are supported. 7.1 Overview The processor LCD controller supports single- or dual-panel displays. Encoded pixel data created by the core is stored in external memory in a frame buffer in 1, 2, 4, 8, or 16-bit increments.
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LCD Controller In active color display mode, the LCD controller can drive TFT displays. When using 1-, 2-, 4-, or 8-bit modes, the LCD’s dither logic is bypassed, and the pixel value is sent from the palette buffer directly to the LCD’s data output pins. 16-bit pixel mode bypasses both the palette and the dither logic. 7.1.
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LCD Controller Figure 7-1 illustrates a simplified, top-level block diagram for the processor LCD Controller. Figure 7-1.
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LCD Controller 7.1.2 Pin Descriptions When the LCD controller is enabled, all of the LCD pins are outputs only. When the LCD controller is disabled, its pins can be use for general-purpose input/output (GPIO). Refer to the System Integration Unit chapter for details. Table 7-1 describes the LCD controller’s pins. For more detailed information, see Section 7.3.5. All of the LCD pins are outputs only. Table 7-1.
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LCD Controller If the LCD controller is being re-enabled, there has not been a reset since the last programming, and the GPIO pins are still configured for LCD Controller functionality, only the registers FDADRx and LCCR0 need to be reprogrammed. The LCD Controller Status Register (LCSR) must also be written to clear any old status flags before re-enabling the LCD controller. See Section 7.6.7 for details. 7.2.2 Disabling the Controller The LCD controller can be disabled in two ways: regular and quick.
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LCD Controller 1, 2, 4, or 8-bits, the FIFO entries are unpacked and used to index the palette RAM to read the color value. In 16-bit passive mode, the entries bypass the palette and go directly to the TMED dither logic. In 16-bit active mode, the pixels are sent directly to the pins. 7.3.2 Lookup Palette The internal palette RAM holds up to 256 16-bit color values. Color palette RAM entries are 16 bits wide, with 5 bits of red, 6 bits of green, and 5 bits of blue. Monochrome entries are 8 bits wide.
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LCD Controller Figure 7-3. Compare Range for TMED 255 0 LB=(PixelValue * Frame#) mod 256 + Offset Compare Range 64 192 (LB+PV) mod 256 128 Either of two matrices may be used for each color, chosen by bits 0, 1, and 14 of the TMED Control Register (TCR, Section 7.6.10). Offsets may be selected for the shading of each color to avoid gray color problems. Although these offset values are panel dependent, the recommended values are listed in Section 7.6.
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LCD Controller Figure 7-4.
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LCD Controller 7.3.5.1 Passive Display Timing In passive display mode (LCCR0[PAS] = 0), L_PCLK toggles only when data is being written to the panel. When an entire line of pixels has been sent to the display, L_LCLK is asserted. When an entire frame of pixels has been sent to the display, L_FCLK is asserted. If an output FIFO underrun occurs (i.e., the LCD controller runs out of data), L_PCLK stalls until valid data is available.
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LCD Controller unpacked into individual pixel encodings of 1, 2, 4, 8, or 16 bits each. After the value is removed from the bottom of the FIFO, the entry is invalidated, and all data in the FIFO is shifted down one entry. When four of the entries are empty, a service request is issued to the DMAC.
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LCD Controller Figure 7-5. Palette Buffer Format Individual Palette Entry Bit 15 14 Color 13 12 11 10 9 Red (R) Bit 15 14 13 12 Mono 8 7 6 5 4 3 Green (G) 11 10 9 8 7 2 1 0 1 0 Blue (B) 6 5 unused 4 3 2 Monochrome (M) Little Endian Palette Entry Ordering 4-, 16- or 256-Entry Palette Buffer Bit 31 16 15 0 Base + 0x0 Palette entry 1 Palette entry 0 Base + 0x4 Palette entry 3 Palette entry 2 Entries 4 through 255 do not exist for 1 and 2 bits/pixel.
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LCD Controller Figure 7-7. 2 Bits Per Pixel Data Memory Organization Bit 1 2 bits/pixel Bit 31 30 29 0 Palette Buffer Index<1:0> 28 27 26 ... 7 6 5 4 3 2 1 0 Base + 0x0 Pixel 15 Pixel 14 Pixel 13 ... Pixel 3 Pixel 2 Pixel 1 Pixel 0 Base + 0x4 Pixel 31 Pixel 30 Pixel 29 ... Pixel 19 Pixel18 Pixel 17 Pixel 16 Figure 7-8.
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LCD Controller Figure 7-10. 16 Bits Per Pixel Data Memory Organization - Passive Mode ) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Raw Pixel Data<15:0> 16 bits/pixel Red Data<4:0> Bit Note: Green Data<5:0> 31 16 Blue Data<4:0> 15 0 Base + 0x0 Pixel 1 Pixel 0 Base + 0x4 Pixel 3 Pixel 2 For passive 16 bits per pixel operation, the Raw Pixel Data must be organized as shown above. Figure 7-11.
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LCD Controller Use the following equation to calculate the total size of the frame buffer (in bytes). This calculation is used to encode the length of the frame buffer in the DMA descriptors (Section 7.6.5.4). The first term is the size required for the encoded pixel values. “Lines” is the number of lines for the display. “Pixels” is the number of pixels per line. Use the actual line/pixel count, not minus 1 as in the LCCR registers.
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LCD Controller Figure 7-12.
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LCD Controller Figure 7-14. Passive Mode Pixel Clock and Data Pin Timing L_FCLK L_LCLK PCP = 0 L_PCLK LDD[3:0] Pixels 0 .. 3 Pixels 4 .. 7 Pixels 8 .. 11 Pixels 12 .. 15 Pixels 16 .. 19 PCP - Pixel Clock Polarity 0 - Pixels sampled from data pins on rising edge of clock 1 - Pixels sampled from data pins on falling edge of clock For PCP = 1 the L_PCLK waveform is inverted, but the timing is identical. Figure 7-15.
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LCD Controller Figure 7-16. Active Mode Pixel Clock and Data Pin Timing L_FCLK (VSYNC) L_LCLK (HSYNC) L_BIAS (OE) PCP = 0 L_PCLK LDD[15:0] Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel 4 PCP - Pixel Clock Polarity 0 - Pixels sampled from data pins on rising edge of clock. 1 - Pixels sampled from data pins on falling edge of clock . For PCP = 1 the L_PCLK waveform is inverted, but the timing is identical. 7.
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LCD Controller The DMA descriptor addresses are initially programmed by software. After that, the other DMA registers are programmed by the hardware. Section 7.6.5 provides a complete description of how the DMA is programmed.
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LCD Controller value that causes the FIFO to wait from 0 to 255 clock cycles after the completion of one DMA request to the start of the next request. When PDD=0x00, the FIFO DMA request delay function is disabled. LCD Quick Disable Interrupt Mask (QDM) — used to mask interrupt requests that are asserted after the LCD Enable bit (ENB) is cleared and the DMAC finishes the current burst transfer. The LCD controller immediately stops requesting new data and the current frame is not completed.
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LCD Controller The LCD pin timing changes when active mode is selected. Timing of each pin is described in subsequent bit-field sections for both passive and active mode. The LCD controller can be configured in active color display mode and used with an external DAC and optionally an external palette to drive a video monitor. Only monitors that implement the RGB data format can be used. The LCD controller does not support the NTSC standard.
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LCD Controller status register (LCSR) is set, an interrupt request is made to the interrupt controller. When SFM=1, the interrupt is masked and the state of the SOF status bit is ignored by the interrupt controller. Setting SFM does not affect the current state of SOF or the LCD controller’s ability to set and clear SOF, it only blocks the generation of the interrupt request.
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LCD Controller Table 7-2. LCD Controller Data Pin Utilization (Sheet 2 of 2) Color/Monochrome Panel Single/ Dual Panel Passive/ Active Panel Screen Portion Top Color Dual Passive Color Single Active Pins L_DD[7:0] Bottom L_DD[15:8] Whole L_DD[15:0] † Double-pixel data mode (DPD) = 1. Figure 7-18.
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LCD Controller Color/Monochrome Select (CMS) — selects whether the LCD controller operates in color or monochrome mode. When CMS=0, color mode is selected. Palette entries are 16 bits wide (5-bits red, 6-bits green, 5-bits blue), 8 data pins are enabled for single-panel mode, 16 data pins are enabled for dual-panel mode, and all three dither blocks are used, one each for the red, green, and blue pixel components.
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LCD Controller Table 7-3.
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LCD Controller Beginning-of-Line Pixel Clock Wait Count (BLW) — used to specify the number of dummy pixel clocks to insert at the beginning of each line or row of pixels. After the line clock for the previous line has been negated, the value in BLW is used to count the number of pixel clocks to wait before starting to output the first set of pixels in the next line. BLW generates a wait period ranging from 1 to 256 pixel clock cycles.
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LCD Controller Table 7-4.
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LCD Controller In passive mode, EFW must be set to zero so that no EOF wait states are generated. Use VSW exclusively in passive mode to insert line clock wait states, which allow the LCD controller’s DMAC to fill the palette and insert additional pixels before the start of the next frame.
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LCD Controller This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 7-5.
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LCD Controller 0b011 = 8-bit pixels 0b100 = 16-bit pixels 0b101–0b111 = reserved Output Enable Polarity (OEP) — In active display mode (LCCR0[PAS] = 1), the OEP bit selects the active and inactive states of the output enable signal (L_BIAS). In this mode, the AC bias pin serves as an enable that signals the off-chip device when data is actively being driven using the pixel clock, which continuously toggles in active mode. When OEP = 0, L_BIAS is active high and inactive low.
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LCD Controller In active display mode (LCCR0[PAS] = 1), L_BIAS is the output enable signal. However, signalling of the API interrupt may still occur. The ACB bit field can be used to count line clock pulses in active mode. When the programmed number of line clock pulses occurs, an internal signal is toggled that is used to decrement the 4-bit counter used by the API interrupt logic. Once this internal signal toggles the programmed number of times, as specified by API, an interrupt is generated.
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LCD Controller LCLK PixelClock = -----------------------------2 ( PCD + 1 ) LCLK PCD = ------------------------------------- – 1 2 ( PixelClock ) where LCLK = LCD/Memory Clock PCD = LCCR3[7:0] This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 7-6.
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LCD Controller Table 7-6. LCCR3 Bit Definitions (Sheet 2 of 2) Physical Address 0x4400_000C Bits X 0 0 0 0 VSP X HSP X PCP X BPP OEP reserved Reset LCD Controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 DPC Bit LCD Controller Control Register 3 0 0 0 0 API 0 0 0 8 7 6 5 ACB 0 0 0 Name 0 0 0 4 3 2 1 0 0 0 0 PCD 0 0 0 0 0 0 0 0 Description AC bias Pin transitions per Interrupt.
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LCD Controller word[1] contains the value for FSADRx word[2] contains the value for FIDRx word[3] contains the value for LDCMDx Software must write the location of the first descriptor to FDADRx before enabling the LCD controller. Once the controller is enabled, the first descriptor is read, and all four registers are written by the DMAC. The next frame descriptor pointed to by FDADRx is loaded into the registers for the associated DMA channel after all data for the current descriptor has been transferred.
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LCD Controller These are read-only registers. Ignore reads from reserved bits. Table 7-8. FSADRx Bit Definitions Physical Address channel 0: 0x4400_0204 channel 1: 0x4400_0214 Bit FSADR0 FSADR1 LCD Controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? Frame Source Address Reset ? ? ? ? ? ? ? Bits Name 31:0 Frame Source Address 7.6.5.
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LCD Controller 7.6.5.5 LCD DMA Command Registers (LDCMDx) LDCMDx, shown in Table 7-10, correspond to DMA channels 0 and 1 and contain configuration fields and the length of the current descriptor for the DMA channel. On reset, the bits in these register are initialized to zero. Reserved bits must be written with zeros and reads from reserved bits must be ignored. These read-only registers are loaded indirectly via the frame descriptors, as described in Section 7.6.5.1.
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LCD Controller Table 7-10. LDCMDx Bit Definitions Physical Address channel 0: 0x4400_020C channel 1: 0x4400_021C X X X X EOFINT X reserved SOFINT reserved Reset LCD Controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 PAL Bit LDCMD0 LDCMD1 0 X 0 0 Bits Name 31:27 — X X 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 LEN 0 0 0 0 0 0 0 0 0 0 0 0 Description reserved Load Palette: 26 PAL 0 = DMA in progress is not the palette buffer.
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LCD Controller 7.6.6 LCD DMA Frame Branch Registers (FBRx) FBRx, one for each DMA channel, shown in Table 7-11, contain the addresses, aligned on a 4-byte boundary, of the descriptors to branch to. When BRA is set, the Frame Descriptor Address Register is ignored. The next descriptor is fetched from the address in FBRx[31:4], regardless of whether frame data or palette RAM data is being processed.
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LCD Controller 7.6.7 LCD Controller Status Register (LCSR) LCSR, shown in Table 7-12, contains bits that signal: • • • • • Underrun errors for both the input and output FIFOs AC bias pin transition count LCD disable and quick disable DMA start/end frame and branch status DMA transfer bus error conditions. Unless masked, each of these hardware-detected events signals an interrupt request to the interrupt controller. Two bits, BER and ABC, generate nonmaskable interrupts.
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LCD Controller panels. When OU is set, an interrupt request is made to the interrupt controller if it is unmasked (LCCR0[OUM] = 0). Output FIFO underruns are more important that Input FIFO underruns, because they affect the panel. Input FIFO Underrun Upper Panel Status (IUU) — set when the upper panel’s input FIFO is completely empty and the LCD controller’s pixel unpacking logic attempts to fetch data from the FIFO. It is cleared by writing one to the bit.
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LCD Controller Table 7-12.
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LCD Controller Table 7-12.
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LCD Controller 7.6.9 TMED RGB Seed Register (TRGBR) TRGBR, shown in Table 7-14 contains the three (red, green, blue) eight-bit seed values used by the TMED algorithm. This value is added into the modified pixel data value as an offset in creating the lower boundary for the algorithm. These values are used during the dithering process for passive (DSTN) displays. The default, recommended setting is 0x00AA5500. This setting provides superior display results in most cases. This is a write-only register.
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LCD Controller 7.6.10 TMED Control Register (TCR) TCR, shown in Table 7-15, selects various options available in the TMED dither algorithm. There are two Temporal Modulated Energy Distribution algorithms that can be used. The default, recommended setting is 0x0000754F. This setting provides superior display results in most cases. For more details on the effects of the individual fields within this register, please refer to Section 7.3.3.
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LCD Controller Table 7-15.
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LCD Controller Table 7-16.
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LCD Controller 7-46 Intel® PXA255 Processor Developer’s Manual
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Synchronous Serial Port Controller 8 This chapter describes the Synchronous Serial Port Controller’s (SSPC) signal definitions and operation for the PXA255 processor usage. 8.1 Overview The SSPC is a full-duplex synchronous serial interface and can connect to a variety of external analog-to-digital (A/D) converters, audio and telecom codecs, and other devices that use serial protocols for transferring data.
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Synchronous Serial Port Controller SSPEXTCLK is an external clock (input through GPIO27) that replaces the standard 3.6864 MHz clock used to generate the serial bit-rate clock (SSPSCLK). The external clock is internally divided by 2 and then further divided by the value in SSCR0[SCR]. If SSP operation is disabled, the five SSP pins are available for GPIO use. See Chapter 4, “System Integration Unit” for details on configuring pin direction and interrupt capabilities. 8.
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Synchronous Serial Port Controller • SSPRXD–Receive signal for inbound data, from peripheral to system. A data frame can be configured to contain from 4 to 16 bits. Serial data is transmitted most significant bit first. The SSPC supports three formats: Motorola SPI, Texas Instruments SSP, and National Microwire. The three formats have significant differences, as described below.
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Synchronous Serial Port Controller . Figure 8-1. Texas Instruments’ Synchronous Serial Frame* Format SSPSCLK ... SSPSFRM ... SSPTXD Bit Bit ... Bit<1> Bit<0> SSPRXD Bit Bit ... Bit<1> Bit<0> MSB 4 to 16 Bits LSB Single Transfer SSPSCLK ... ... ... ... SSPSFRM SSPTX /RX Bit<0> Bit Bit ... Bit<1> Bit<0> Bit Bit ... Bit<1> Bit<0> Continuous Transfers 8.4.1.2 SPI Format Details The SPI format has four sub-modes.
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Synchronous Serial Port Controller Figure 8-2 shows one of the four configurations for the Motorola SPI frame format for single and back-to-back frame transmissions. Figure 8-2. Motorola SPI* Frame Format SSPSCLK ... SSPSFRM ... SSPTXD Bit SSPRXD Bit Bit ... Bit<1> Bit<0> Bit ... Bit<1> Bit<0> MSB 4 to 16 Bits LSB Single Transfer SSPSCLK ... ... ... ... SSPSFRM SSPTX /RX Bit<0> Bit Bit ... Bit<1> Bit<0> Bit Bit ...
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Synchronous Serial Port Controller Figure 8-3 shows the National Microwire frame format with 8-bit command words for single and back-to-back frame transmissions. Figure 8-3. National Microwire* Frame Format SSPSCLK ... ... ... ... SSPSFRM SSPTXD Bit<7> ... Bit<0> 8-Bit Control SSPRXD ... 1 Clk ... Bit ... Bit<0> 4 to 16 Bits Single Transfer SSPSCLK ... ... ... ... ... ... SSPSFRM SSPTXD Bit<0> ... Bit<7> ... Bit<0> 1 Clk SSPRXD ... 1 Clk Bit ... Bit<0> ... Bit ..
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Synchronous Serial Port Controller 8.5 FIFO Operation and Data Transfers Transmit and receive serial data use independent FIFOs. FIFOs are filled or emptied by programmed I/O or DMA bursts that the DMAC initiates. Bursts may be 4 or 8 half-words in length during transmission or reception. 8.5.1 Using Programmed I/O Data Transfers Data words are 32 bits wide, but only 16-bit samples are transferred. Only the lower 2 bytes of a 32-bit word have valid data.
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Synchronous Serial Port Controller 8.7 SSP Serial Port Registers The SSPC has five registers: two control, one data, one status, and one “reserved” register: • The SSPC Control Registers (SSCR0 and SSCR1) are used to program the baud rate, data length, frame format, data transfer mechanism, and port enabling. They also control the FIFO “fullness” threshold that triggers an interrupt. These registers must be written before the SSP is enabled after reset and must only be changed when SSP is disabled.
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Synchronous Serial Port Controller Table 8-2.
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Synchronous Serial Port Controller transmit FIFO. The transmit logic in the SSPC left-justifies the data sample according to the DSS bits before the sample is transmitted. Data sizes of 1, 2, and 3 bits are reserved and produce unpredictable results in the SSPC. In National Microwire frame format, this bit field selects the size of the received data. The size of the transmitted command data is either 8-bit or 16-bit as selected by the MWDS bit in SSCR1. 8.7.1.
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Synchronous Serial Port Controller 8.7.1.5 Serial Clock Rate (SCR) The 8-bit serial clock rate (SCR) bit-field is used to select the SSPC bit rate. The SSPC has 256 bit rates, from 7.2 Kbps to 1.8432 Mbps. The serial clock generator uses the internal 3.6864 MHz clock or an external clock provided through SSPEXTCLK. The clock is divided by 2, then divided by the programmable SCR value (0 to 255) plus 1 to generate the serial clock (SSPSCLK).
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Synchronous Serial Port Controller Table 8-3. SSCR1 Bit Definitions (Sheet 2 of 2) Synchronous Serial Port Controller Bits Name 9:6 (Transmit FIFO Threshold) 13:10 (Receive FIFO Threshold) 31:14 — TFT RFT 8.7.2.
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Synchronous Serial Port Controller Note: 8.7.2.4 Loop back mode cannot be used with Microwire frame format. Serial Clock Polarity (SPO) The serial clock polarity bit (SPO) selects the SSPSCLK signal’s inactive state in the Motorola SPI format (FRF=00). For SPO=0, the SSPSCLK is held low in the inactive or idle state when the SSP is not transmitting/receiving data. When the SPO bit is set to a 1, the SSPSCLK is held high during the inactive/idle state.
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Synchronous Serial Port Controller Figure 8-4. Motorola SPI* Frame Formats for SPO and SPH Programming SSPRXD Bit MSB Bit ... Bit<1> 4 to 16 Bits Bit<0> LSB SPH = 0 SSPSCLK SPO=0 ... SSPSCLK SPO=1 ... SSPSFRM ... SSPTXD SSPRXD Bit Bit MSB Bit ... Bit<1> Bit<0> Bit ... Bit<1> Bit<0> 4 to 16 Bits LSB SPH = 1 8.7.2.
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Synchronous Serial Port Controller Table 8-4. TFT and RFT Values for DMA Servicing DMA Burst Size TFT Value RFT Value Min Max Min Max 8 Bytes 0 11 3 15 16 Bytes 0 7 7 15 This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. 8.7.3 SSP Data Register (SSDR) SSDR, shown in Table 8-5, is a single address location that can be accessed by read/write data transfers. Transfers can be single transfers, 4 half-word bursts, or 8 half-word bursts.
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Synchronous Serial Port Controller 8.7.4 SSP Status Register (SSSR) The SSP Status Register (SSSR) is shown in Table 8-6. The SSSR contains bits that signal overrun errors and transmit and receive FIFO service requests. These hardware-detected events signal an interrupt request to the interrupt controller.
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Synchronous Serial Port Controller Table 8-6.
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Synchronous Serial Port Controller 8.7.4.2 Receive FIFO Not Empty Flag (RNE) This non-interruptible bit is set when the receive FIFO contains one or more entries and is cleared when the FIFO is empty. Because CPU interrupt requests are only made when the Receive FIFO Threshold has been met or exceeded, the RNE bit can be polled when programmed I/O removes remaining bytes of data from the receive FIFO. This bit does not request an interrupt. 8.7.4.
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Synchronous Serial Port Controller 8.7.4.8 Receive FIFO Level (RFL) This bit indicates the one less than number of entries in the Receive FIFO. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. 8.8 SSP Controller Register Summary Table 8-7 shows the SSP registers associated with the SSP controller and their physical addresses. Table 8-7.
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Synchronous Serial Port Controller 8-20 Intel® PXA255 Processor Developer’s Manual
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I2C Bus Interface Unit 9 This chapter describes the Inter-Integrated Circuit (I2C) bus interface unit, including the operation modes and setup for the PXA255 processor. 9.1 Overview The I2C bus was created by the Phillips Corporation and is a serial bus with a two-pin interface. The SDA data pin is used for input and output functions and the SCL clock pin is used to control and reference the I2C bus. The I2C unit allows the processor to serve as a master and slave device that resides on the I2C bus.
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I2C Bus Interface Unit Table 9-2. I2C Bus Definitions I2C Device Definition 2 Transmitter Sends data to the I C bus. Receiver Receives data from the I2C bus. Master Initiates a transfer, generates the clock signal, and terminates the transactions. Slave Device addressed by a master. Multi-master More than one master can attempt to control the bus at the same time without corrupting the message.
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I2C Bus Interface Unit 9.3.1 Operational Blocks The I2C unit is connected to the peripheral bus. The processor interrupt mechanism can be used to notify the CPU that there is activity on the I2C bus. Polling can be used instead of interrupts. The I2C unit consists of the two wire interface to the I2C bus, an 8-bit buffer for passing data to and from the processor, a set of control and status registers, and a shift register for parallel/serial conversions.
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I2C Bus Interface Unit When the I2C unit receives an address that matches the 7-bit address found in the I2C Slave Address Register (ISAR) or the general call address (see Section 9.4.7), the interface either remains in slave-receive mode or transitions to slave-transmit mode. The Read/Write bit (R/nW) determines which mode the interface enters. The R/nW bit is the least significant bit of the byte containing the slave address.
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I2C Bus Interface Unit Figure 9-2 shows the relationship between the SDA and SCL lines for START and STOP conditions. ~ Figure 9-2. Start and Stop Conditions ~ ~ SDA SCL Start Condition 9.3.3.1 Stop Condition START Condition The START condition (ICR[START]=1, ICR[STOP]=0) initiates a master transaction or repeated START. Before it sets the START ICR bit, software must load the target slave address and the R/ nW bit in the IDBR (see Section 9.9.2).
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I2C Bus Interface Unit Figure 9-3.
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I2C Bus Interface Unit 9.4 I2C Bus Operation The I2C unit transfers data in 1-byte increments and always follows this sequence: 1) START 2) 7-bit Slave Address 3) R/nW Bit 4) Acknowledge Pulse 5) 8 Bits of Data 6) ACK/NAK Pulse 7) Repeat of Steps 5 and 6 for required number of bytes 8) Repeated START (Repeat Step 1) or STOP 9.4.1 Serial Clock Line (SCL) Generation When the I2C unit is in master-transmit or master-receive mode, it generates the I2C clock output.
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I2C Bus Interface Unit 9.4.2.1 Addressing a Slave Device As a master device, the I2C unit must compose and send the first byte of a transaction. This byte consists of the slave address for the intended device and a R/nW bit for transaction definition. The MSB is transmitted first. The slave address and the R/nW bit are written to the IDBR (see Figure 9-4). Figure 9-4.
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I2C Bus Interface Unit Figure 9-5. Acknowledge on the I2C Bus ∼ SDA released ∼ Data Output by Transmitter (SDA) ∼ SDA pulled low by Receiver (ACK) ∼ Data Output by Receiver (SDA) SCL from Master Start Condition 1 2-7 8 9 Clock Pulse for Acknowledge In master-transmit mode, if the target slave-receiver device cannot generate the acknowledge pulse, the SDA line remains high.
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I2C Bus Interface Unit 9.4.4.1 SCL Arbitration Each master on the I2C bus generates its own clock on the SCL line for data transfers. As a result, clocks with different frequencies may be connected to the SCL line. Because data is valid when a clock is in the high period, bit-by-bit arbitration requires a defined clock synchronization procedure. Clock synchronization is through the wired-AND connection of the I2C interfaces to the SCL line.
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I2C Bus Interface Unit Figure 9-7. Arbitration Procedure of Two Masters Transmitter 1 Leaves Arbitration Data 1 SDA Data 1 Data 2 SDA SCL If the I 2C unit loses arbitration as the address bits are transferred and it is not addressed by the address bits, the I2C unit resends the address when the I2C bus becomes free. A resend is possible because the IDBR and ICR registers are not overwritten when arbitration is lost.
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I2C Bus Interface Unit 9.4.5 Master Operations When software initiates a read or write on the I2C bus, the I2C unit transitions from the default slave-receive mode to master-transmit mode. The 7-bit slave address and the R/nW bit follow the start pulse. After the master receives an acknowledge, the I2C unit enters one of two master modes: • Master-Transmit — I2C unit writes data • Master-Receive — I2C unit reads data The CPU writes to the ICR register to initiate a master transaction.
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I2C Bus Interface Unit Table 9-5. Master Transactions (Sheet 2 of 2) I2C Master Action Mode of Operation Definition • I2C master operation data transmit mode. Write one data byte to the IDBR Master-transmit only Wait for Acknowledge from slavereceiver Master-transmit only • Occurs when the ISR[ITE] bit is set and the ICR[TB] bit is clear. If the IDBR Transmit Empty Interrupt is enabled, it is signalled to the processor.
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I2C Bus Interface Unit . Figure 9-8. Master-Receiver Read from Slave-Transmitter START Slave Address R/nW 1 First Byte Read Data Byte ACK Data Byte ACK ACK STOP N Bytes + ACK Slave to Master Master to Slave Default Slave-Receive Mode \ Figure 9-9.
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I2C Bus Interface Unit Table 9-6. Slave Transactions I2C Slave Action Mode of Operation Definition • I2C unit monitors all slave address transactions. • ICR[IUE] bit must be set. Slave-receive (default mode) Slave-receive only • I2C unit monitors bus for START conditions. When a START is detected, the interface reads the first 8 bits and compares the most significant seven bits with the 7-bit ISAR and the general call address (0x00). If there is a match, the I2C unit sends an ACK.
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I2C Bus Interface Unit Figure 9-11. Master-Transmitter Write to Slave-Receiver START Slave Address First Byte Master to Slave R/nW 0 Data Byte ACK Write ACK Data Byte ACK STOP NAK STOP N Bytes + ACK Slave to Master Figure 9-12. Master-Receiver Read to Slave-Transmitter START Slave Address First Byte R/nW 1 Data Byte ACK Read ACK Data Byte N Bytes + ACK Default Slave-Receive Mode Slave to Master Master to Slave Figure 9-13.
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I2C Bus Interface Unit The I2C unit supports sending and receiving general call address transfers on the I2C bus. When software sends a general call message from the I2C unit, it must set the ICR[GCD] bit to prevent the I2C unit from responding as a slave. If the ICR[GCD] is not set, the I2C bus enters an indeterminate state.
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I2C Bus Interface Unit 9.5 Slave Mode Programming Examples 9.5.1 Initialize Unit 1. Set the slave address in the ISAR. 2. Enable desired interrupts in the ICR. 3. Set the ICR[IUE] bit to enable the I2C unit. 9.5.2 Write n Bytes as a Slave 1. When a Slave Address Detected interrupt occurs. Read ISR: Slave Address Detected (1), Unit Busy (1), R/nW bit (1), ACK/NAK (0) 2. Write a 1 to the ISR[SAD] bit to clear the interrupt. 3. Return from interrupt. 4. Load data byte to transfer in the IDBR. 5.
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I2C Bus Interface Unit 5. When an IDBR Receive Full interrupt occurs. Read ISR: IDBR Receive Full (1), ACK/NAK (0), R/nW bit (0) 6. Read IDBR to get the received byte. 7. Write a 1 to the ISR[IRF] bit to clear interrupt. 8. Return from interrupt. 9. Repeat steps 4 to 8 for n-1 times. Once the IDBR is full, the I2C unit will keep SCL low until the data is read. 10. Set ICR[TB] bit to release I2C bus and allow next transfer. 11. When a Slave Stop Detected interrupt occurs.
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I2C Bus Interface Unit 9.6.3 Read 1 Byte as a Master 1. Load target slave address and R/nW bit in the IDBR. R/nW must be 1 for a read. 2. Initiate the write. Set ICR[START], clear ICR[STOP], clear ICR[ALDIE], set ICR[TB] 3. When an IDBR Transmit Empty interrupt occurs. Read ISR: IDBR Transmit Empty (1), Unit busy (1), R/nW bit (1) 4. Write a 1 to the ISR[ITE] bit to clear the interrupt. 5. Initiate the read. Clear ICR[START], set ICR[STOP], set ICR[ALDIE], set ICR[ACKNAK], set ICR[TB] 6.
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I2C Bus Interface Unit 16. Write a 1 to the ISR[IRF] bit to clear the interrupt. 17. Read IDBR data. 18. Clear ICR[STOP] and ICR[ACKNAK] bits 9.6.5 Read 2 Bytes as a Master - Send STOP Using the Abort 1. Load target slave address and R/nW bit in the IDBR. R/nW must be 1 for a read. 2. Initiate the write. Set ICR[START], clear ICR[STOP], clear ICR[ALDIE], set ICR[TB] 3. When an IDBR Transmit Empty interrupt occurs. Read ISR: IDBR Transmit Empty (1), Unit busy (1), R/nW bit (1) 4.
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I2C Bus Interface Unit When the ICR[UR] bit is set, the I2C unit resets but the associated I2C MMRs remain intact. When resetting the I2C unit with the ICR’s unit reset, use the following guidelines: 1. Set the reset bit in the ICR register and clear the remainder of the register. 2. Clear the ISR register. 3. Clear reset in the ICR. 9.9 Register Definitions 9.9.1 I2C Bus Monitor Register (IBMR) The IBMR, shown in Table 9-8, tracks the status of the SCL and SDA pins.
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I2C Bus Interface Unit on the acknowledge pulse in receiver mode. After the processor reads the IDBR, the ACK/NAK Control bit is written and the Transfer Byte bit is written, allowing the next byte transfer to proceed to the I2C bus. The IDBR register is 0x00 after reset. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 9-9.
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I2C Bus Interface Unit Table 9-10. ICR Bit Definitions (Sheet 2 of 3) 0 0 0 0 0 0 0 0 0 0 1 0 START 0 2 STOP 0 3 TB 0 4 ACKNAK 0 5 MA 0 6 SCLE 0 7 IUE 0 8 GCD 0 BEIE 0 IRFIE 0 SSDIE 0 ALDIE 0 SADIE 0 UR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 reserved Reset I2C Bus Interface Unit FM Bit I2C Control Register ITEIE Physical Address 4030_1690 0 0 0 0 0 0 0 0 Bus Error Interrupt Enable: 0 = Disable interrupt.
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I2C Bus Interface Unit Table 9-10.
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I2C Bus Interface Unit Table 9-11. ISR Bit Definitions (Sheet 1 of 2) Physical Address 4030_1698 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SAD GCAD IRF ITE ALD SSD IBB UB ACKNAK RWM I2C Bus Interface Unit BED Bit I2C Status Register 0 0 0 0 0 0 0 0 0 0 0 reserved Reset 0 0 0 31:11 0 0 0 0 — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reserved Bus Error Detected: 0 = No error detected.
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I2C Bus Interface Unit Table 9-11. ISR Bit Definitions (Sheet 2 of 2) I2C Bus Interface Unit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UB 0 1 ACKNAK 0 2 IBB 0 3 SSD 0 4 ALD 0 5 ITE 0 6 IRF Reset 7 GCAD reserved 8 SAD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BED Bit I2C Status Register RWM Physical Address 4030_1698 0 0 0 0 0 0 0 0 0 0 ACK/NAK Status: 1 0 = I2C unit received or sent an ACK on the bus.
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I2C Bus Interface Unit 9-28 Intel® PXA255 Processor Developer’s Manual
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10 UARTs This chapter describes the universal asynchronous receiver/transmitter (UART) serial ports. The serial ports are controlled via direct memory access (DMA) or programmed I/O. The PXA255 processor has four UARTs: Full Function UART (FFUART), Bluetooth UART (BTUART), Standard UART (STUART) and Hardware UART (HWUART). The HWUART is covered in Chapter 17. The UARTs use the same programming model. 10.
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UARTs 10.2 Overview Each serial port contains a UART and a slow infrared transmit encoder and receive decoder that conforms to the IRDA Serial Infrared (SIR) Physical Layer Link Specification. Each UART performs serial-to-parallel conversion on data characters received from a peripheral device or a modem and parallel-to-serial conversion on data characters received from the processor. The processor can read a UART’s complete status during functional operation.
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UARTs 10.3 Signal Descriptions Table 10-1 lists and describes each external signal that is connected to a UART module. The pins are connected through the System Integration Unit to GPIOs. Refer to Section 4.1, “GeneralPurpose I/O” on page 4-1 for details on the GPIOs. Table 10-1. UART Signal Descriptions (Sheet 1 of 2) Name Type Description RXD Input SERIAL INPUT: Serial data input to the receive shift register. In infrared mode, it is connected to the infrared receiver input.
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UARTs Table 10-1. UART Signal Descriptions (Sheet 2 of 2) Name Type nRI Input Description RING INDICATOR: When low, indicates that the modem or data set has received a telephone ringing signal. The nRI signal is a Modem Status input whose condition can be tested by reading Bit 6 (RI) of the MSR. Bit 6 is the complement of the nRI signal. Bit 2, the trailing edge of ring indicator (TERI), of the MSR indicates whether the nRI input signal has changed from low to high since the MSR was last read.
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UARTs or if odd parity is enabled and the data byte has an even number of ones. The data frame ends with one, one and a half or two stop bits, as programmed by software. The stop bits are represented by one, one and a half, or two successive bit periods of a logic one. Each UART has two FIFOs: one transmit and one receive. The transmit FIFO is 64 bytes deep and eight bits wide. The receive FIFO is 64 bytes deep and 11 bits wide. Three bits are used for tracking errors.
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UARTs . Table 10-2. UART Register Addresses as Offsets of a Base 10.4.2.
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UARTs 10.4.2.2 Transmit Holding Register (THR) In non-FIFO mode, the THR, shown in Table 10-4, holds the data byte that is to be transmitted next. When the TSR is emptied, the contents of the THR are loaded in the TSR and the LSR[TDRQ] is set to a 1. In FIFO mode, a write to the THR puts data into the top of the FIFO. The data at the front of the FIFO is loaded to the TSR when that register is empty. This is a write-only register. Write zeros to reserved bits. Table 10-4.
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UARTs Table 10-5. DLL Bit Definitions UART 0 0 0 0 0 0 Bits Name 31:8 — 7:0 DLL[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 2 1 0 DLL0 0 4 DLL1 Reset 5 DLL2 0 reserved 6 DLL3 7 DLL4 8 DLL5 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 DLL6 Bit Divisor Latch Low Register DLL7 Base (DLAB=1) 0 0 0 0 0 0 4 3 2 1 0 Description reserved Low byte compare value to generate baud rate. Table 10-6.
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UARTs Bit 7 of the IER is used to enable DMA requests. The IER also contains the unit enable and NRZ coding enable control bits. Bits 7 through 4 are used differently from the standard 16550 register definition. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 10-7.
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UARTs In FIFO mode, the “Received Data is available” interrupt (Priority Level 2) takes priority over the “Character Timeout Indication” interrupt (Priority Level 2). For example, if the UART is in FIFO mode and FIFO Control Register[ITL] = 0b00, this will cause the UART to generate an interrupt when there is one byte in the FIFO. In this scenario, if there is one byte in the FIFO, an interrupt is generated, and IIR[3:0] = 0b0100, which indicates that Received Data is available.
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UARTs Table 10-9.
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UARTs Table 10-10. Interrupt Identification Register Decode (Sheet 2 of 2) Interrupt ID Bits 1 1 0 0 0 10.4.2.
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UARTs Table 10-11. FCR Bit Definitions (Sheet 2 of 2) 0 0 0 Bits 2 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 4 0 0 0 3 2 1 0 TRFIFOE 0 reserved Reset 6 RESETRF 7 reserved 8 RESETTF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 reserved UART ITL Bit FIFO Control Register reserved Base+0x08 0 0 0 0 Name Description RESETTF Reset transmitter FIFO: When RESETTF is set to 1, all the bytes in the transmitter FIFO are cleared.
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UARTs Table 10-12.
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UARTs 10.4.2.8 Line Status Register (LSR) The LSR, shown in Table 10-13, provides data transfer status information to the processor. In non-FIFO mode, LSR[4:2]: parity error, framing error, and break interrupt, show the error status of the character that has just been received. In FIFO mode, LSR[4:2] show the status bits of the character that is currently at the front of the FIFO. LSR[4:1] produce a receiver line status interrupt when the corresponding conditions are detected and the interrupt is enabled.
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UARTs Table 10-13. LSR Bit Definitions (Sheet 2 of 3) UART 0 0 Bits 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name TDRQ 0 0 0 0 0 0 1 1 3 2 1 0 DR 0 4 OE Reset 5 PE 0 reserved 6 BI 7 FE 8 TEMT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 TDRQ Bit Line Status Register FIFOE Base+0x14 0 0 0 0 0 Description Transmit Data Request: Indicates that the UART is ready to accept a new character for transmission.
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UARTs Table 10-13.
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UARTs 10.4.2.9 Modem Control Register (MCR) The MCR, shown in Table 10-14, uses the modem control pins nRTS and nDTR to control the interface with a modem or data set. The MCR also controls the Loopback mode. Loopback mode must be enabled before the UART is enabled. The differences between UARTs specific to this register are described in Section 10.5.1. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 10-14.
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UARTs Table 10-14. MCR Bit Definitions (Sheet 2 of 2) 8 7 6 5 4 RTS DTR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OUT1 UART OUT2 Bit Modem Control Register LOOP Base+0x10 0 0 0 0 0 0 0 0 0 reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 2 1 0 Read/Write Bits Name 2 OUT1 1 RTS 0 DTR Description Test bit. This bit is used only in Loopback mode. It is ignored otherwise.
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UARTs Table 10-15.
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UARTs 10.4.2.11 Scratchpad Register (SPR) The SPR, shown in Table 10-16, has no effect on the UART. It is intended as a scratchpad register for use by the programmer. It is included for 16550 compatibility. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 10-16. SPR Bit Definitions Base+0x1C UART 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 reserved Reset 0 10.4.
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UARTs After the processor reads one character from the receive FIFO or a new start bit is received, the character timeout indication interrupt is cleared and the timeout is reset. If a character timeout indication interrupt has not occurred, the timeout is reset when a new character is received or the processor reads the receive FIFO. 10.4.3.3 Transmit Interrupt Transmit interrupts can only occur when the transmit FIFO and transmit interrupt are enabled.
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UARTs Note: 10.4.5.1 Ensure that the DMAC has finished previous receive DMA requests before the error interrupt handler begins to clear the errors from the FIFO. Trailing Bytes in the Receive FIFO Trailing bytes occur when the number of entries in the receive FIFO is less than its trigger level and no more data is being received. In such a case, a receive DMA request is not generated. To read the trailing bytes follow these steps: 1. Wait for a character timeout indication interrupt.
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UARTs Table 10-17.
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UARTs Figure 10-3. IR Transmit and Receive Example UART TRANSMIT SHIFT VALUE START BIT 1 0 0 0 1 1 0 0 STOP BIT IR ENCODER OUTPUT (TXD PIN VALUE) RXD PIN VALUE IR DECODER OUTPUT UART RECEIVE START BIT 1 0 0 0 1 1 0 SHIFT VALUE 0 STOP BIT The top line in Figure 10-3 shows an asynchronous transmission as it is sent from the UART. The second line shows the pulses generated by the IR encoder at the TXD pin.
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UARTs the Transmit FIFO will not be held. Only add data to the Transmit FIFO while not receiving. To start transmission, the RCVEIR bit must be cleared. To disable SIR, disable the IrDA LED first, if possible. Second, set the TXD GPIO pin to the infrared LED's default state using the GPCR/GPSR registers. Next, change the TXD pin from alternate function to GPIO mode. Now the SIR can be disabled without causing spurious transmit pulses. 10.
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UARTs Table 10-19. BTUART Register Summary (Sheet 2 of 2) Register Addresses DLAB Bit Value Name Description 0x4020_001C X BTSPR Scratch Pad Register 0x4020_0020 X BTISR Infrared Selection register (read/write) 0x4020_0000 1 BTDLL Divisor Latch Low register (read/write) 0x4020_0004 1 BTDLH Divisor Latch High register (read/write) Table 10-20.
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UARTs 10.5.1 UART Register Differences The default descriptions for BTMCR, BTMSR and STMCR are modified as shown in Table 10-21. . Table 10-21.
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Fast Infrared Communication Port 11 The Fast Infrared Communications Port (FICP) for the PXA255 processor operates at half-duplex and provides direct connection to commercially available Infrared Data Association (IrDA) compliant LED transceivers. The FICP is based on the 4-Mbps IrDA standard and uses fourposition pulse modulation (4PPM) and a specialized serial packet protocol developed for IrDA transmission.
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Fast Infrared Communication Port 11.2.1 4PPM Modulation Four-position pulse modulation (4PPM) is used to transmit data at the high-speed rate, 4.0 Mbps. Data bits are encoded two at a time by placing a single 125 ns light pulse in one of four timeslots. The four timeslots are collectively termed a chip. Bytes are encoded one at a time. They are divided into four individual 2-bit pairings called nibbles. The least significant nibble is transmitted first.
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Fast Infrared Communication Port 11.2.2 Frame Format The frame format used with 4-Mbps transmission is shown in Figure 11-3. Figure 11-3. Frame Format for IrDA Transmission (4.0 Mbps) 64 chips 8 chips Preamble Start Flag 4 chips 4 chips (8 bits) (8 bits) Address Control (optional) (optional) 8180 chips max (2045 bytes) 16 chips Data CRC-32 Preamble - | 1000 | 0000 | 1010 | 1000 |...
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Fast Infrared Communication Port 11.2.6 CRC Field The FICP uses a 32-bit Cyclic Redundancy Check (CRC) to detect bit errors that occur during transmission. The CRC is generated from the address, control, and data fields, and is included in each frame. Transmit and receive logic have separate CRC generators. The CRC computation logic is set to all ones before each frame is transmitted or received and the result is inverted before it is used for comparison or transmission.
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Fast Infrared Communication Port After 16 preambles are transmitted, the start flag is received. The start flag is eight chips long. If any portion of the start flag does not match the encoding, the receive logic signals a framing error and the receive logic returns to hunt mode. When the correct start flag is recognized, each following group of four chips is decoded into a data byte and placed in a 5-byte temporary FIFO that is used to prevent the CRC from being placed in the receive FIFO.
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Fast Infrared Communication Port A minimum of 16 preambles are transmitted for each frame. If data is not available after the sixteenth preamble, additional preambles are transmitted until a byte of valid data resides in the bottom of the transmit FIFO. The preambles are followed by the start flag and the data from the transmit FIFO. Groups of four chips (eight bits) are encoded and loaded in a serial shift register.
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Fast Infrared Communication Port When the transmit FIFO has 32 or more empty bytes, the transmit DMA request and an interrupt (if enabled) are generated and tell the processor to send more data to the FIFO. When the transmit FIFO is full, any more data from the processor is lost.
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Fast Infrared Communication Port 11.3.1 FICP Control Register 0 (ICCR0) The ICCR0, shown in Table 11-2, contains eight valid bit fields that control various functions for 4 Mbps IrDA transmission. The FICP must be disabled (RXE=TXE=0) when ICCR0[ITR] and ICCR0[LBM] are changed. To allow various modes to be changed during active operation, ICCR0[7:2] may be written when the FICP is enabled. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 11-2.
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Fast Infrared Communication Port Table 11-2. ICCR0 Bit Definitions (Sheet 2 of 2) Fast Infrared Communication Port Control Register 0 (ICCR0) 0 0 Bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name 0 0 0 0 0 0 0 0 0 0 3 2 1 0 ITR 0 4 LBM Reset 5 TXE 0 reserved 6 TUS 7 RXE 8 TIE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RIE Bit Fast Infrared Communication Port AME 0x4080_0000 0 0 0 0 Description Transmit enable.
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Fast Infrared Communication Port 11.3.2 FICP Control Register 1 (ICCR1) The ICCR1, shown in Table 11-3, contains the 8-bit address match value field that the FICP uses to selectively receive frames. To allow the address match value to be changed during active receive operation, ICCR1 may be written while the FICP is enabled. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 11-3.
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Fast Infrared Communication Port 11.3.3 FICP Control Register 2 (ICCR2) The ICCR2, shown in Table 11-4, contains two bit fields that control the polarity of the transmit and receive data pins and two bits that determine the trigger level for the receive FIFO. The FICP must be disabled (RXE=TXE=0) when these bits are changed. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 11-4.
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Fast Infrared Communication Port 11.3.4 FICP Data Register (ICDR) The ICDR, shown in Table 11-5, is a 32-bit register and its lower 8 bits are the top entry of the transmit FIFO when the register is written and the bottom entry of the receive FIFO when the register is read. Reads to ICDR access the lower 8 bits of the receive FIFO’s bottom entry. As data enters the top of the receive FIFO, bits 8 – 10 are used as tags to indicate conditions that occur as each piece of data is received.
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Fast Infrared Communication Port 11.3.5 FICP Status Register 0 (ICSR0) The ICSR0, shown in Table 11-6, contains bits that signal the transmit FIFO service request, receive FIFO service request, receiver abort, transmit FIFO underrun, framing error, and the end/ error in receive FIFO conditions. Each of these hardware-detected events signal an interrupt request to the interrupt controller. If a bit signals an interrupt request, it signals the interrupt request as long as the bit is set.
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Fast Infrared Communication Port Table 11-6. ICSR0 Bit Definitions (Sheet 2 of 2) Fast Infrared Communication Port Status Register 0 (ICSR0) 5 0 0 0 0 0 reserved Reset 0 0 0 Bits 0 0 0 0 0 0 0 0 0 0 0 0 0 Name 0 0 0 0 0 0 0 4 3 2 1 0 EIF 6 TUR 7 TFS 8 RAB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RFS Bit Fast Infrared Communication Port FRE 0x4080_0014 0 0 0 0 Description Receiver abort.
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Fast Infrared Communication Port 11.3.6 FICP Status Register 1 (ICSR1) ICSR1, shown in Table 11-7, contains flags that indicate that the receiver is synchronized, the transmitter is active, the transmit FIFO is not full, the receive FIFO is not empty, and that an EOF, CRE, or underrun error has occurred. This is a read-only register. Ignore reads from reserved bits. . Table 11-7.
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Fast Infrared Communication Port 11.4 FICP Register Summary Table 11-8 shows the registers associated with the FICP block and the physical addresses used to access them. Table 11-8.
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USB Device Controller 12 This section describes the Universal Serial Bus (USB) protocol and its implementation-specific options for device controllers for the PXA255 processor. These options include endpoint number, type, and function; interrupts to the core; and a transmit/receive FIFO interface. A working knowledge of the USB standard is vital to using this section effectively. The Universal Serial Bus Device Controller (UDC) is USB-compliant and supports all standard device requests issued by the host.
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USB Device Controller 12-Mbps device and provides the correct polarity for data transmission. The serial bus uses differential signalling to transmit multiple states simultaneously. These states are combined to produce transmit data and various bus conditions, including: Idle, Resume, Start of Packet, End of Packet, Disconnect, Connect, and Reset. 12.2 Device Configuration Table 12-1 shows the device’s configuration. Table 12-1.
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USB Device Controller 12.3.1 Signalling Levels USB uses differential signalling to encode data and to indicate various bus conditions. The USB specification refers to the J and K data states to differentiate between high- and low-speed transmissions. Because the UDC supports only 12 Mbps transmissions, references are only made to actual data state 0 and actual data state 1. By decoding the polarity of the UDC+ and UDC- pins and using differential data, four distinct states are represented.
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USB Device Controller incoming data, which produces the clock. To ensure the receiver is periodically synchronized, six consecutive ones in the serial bit stream trigger the transmitter to insert a zero. This procedure is known as bit stuffing. The receiver logic detects stuffed bits and removes them from incoming data. Bit stuffing causes a transition on the incoming signal at least once every 7 bit times to ensure the baud clock is locked.
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USB Device Controller The Frame Number is an 11-bit field incremented by the host each time a frame is transmitted. When it reaches its maximum value, 2047 (0x7FF), its value rolls over. Frame Number is transmitted in the SOF packet, which the host outputs in 1 ms intervals. Device controllers use the Frame Number field to control isochronous transfers. Data fields are used to transmit the packet data between the host and the UDC. A data field consists of 0 to 1023 bytes.
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USB Device Controller 12.3.4.3 Data Packet Type Data packets follow Token packets and are used to transmit data between the host and UDC. The PID specifies two types of Data packets: DATA0 and DATA1. These Data packets are used to provide a mechanism to ensure that the data sequence between the transmitter and receiver is synchronized across multiple transactions. During the handshake phase, the transmitter and receiver determine which data token type to transmit first.
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USB Device Controller Table 12-7.
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USB Device Controller To assemble control transfers, the host sends a control transaction to tell the UDC what type of control transfer is taking place (control read or control write), followed by one or more data transactions. The setup is the first stage of the control transfer. The device must respond with an ACK or no handshake (if the data is corrupted). The control transaction, by default, uses a DATA0 transfer and each subsequent data transaction toggles between DATA1 and DATA0 transfers.
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USB Device Controller Table 12-11. Host Device Request Summary Request Name SET_FEATURE Enables a specific feature such as device remote wake-up or endpoint stalls. CLEAR_FEATURE Clears or disables a specific feature. SET_CONFIGURATION Configures the UDC for operation. Used after a reset of the Megacell or after a reset has been signalled via the USB. GET_CONFIGURATION Returns the current UDC configuration to the host. SET_DESCRIPTOR Sets existing descriptors or add new descriptors.
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USB Device Controller The direction of the endpoints is fixed. Physically, the UDC only supports interrupt endpoints with a maximum packet size of 8 bytes or less, bulk endpoints with a maximum packet size of 64 bytes or less, and isochronous endpoints with a maximum packet size of 256 bytes or less. To make the processor more adaptable, the UDC supports a total of four configurations.
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USB Device Controller Figure 12-2. Self-Powered Device USB 5V 5 V to 3.3 V GPIOn 470K GPIOx 1.5K USB D+ UDC D+ 0 ohm (optional) USB D- UDC D0 ohm (optional) USB GND Board GND 12.4.1.1 When GPIOn and GPIOx are Different Pins The GPIOn and GPIOx pins can be any GPIO pins. GPIOn must be a GPIO that can wake the device from sleep mode. After a reset, GPIOx is configured as an input. This causes the UDC+ line to float.
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USB Device Controller 12.4.2 Bus-Powered Devices The processor does not support bus-powered devices because it is required to consume less that 500 µA when the host issues a suspend (see Section 7.2.3 of the USB Specification, version 1.1). The processor cannot limit the amount of current it consumes to 500 µA unless it enters sleep mode. When processor enters sleep mode it resets the USB registers and does not respond to its host-assigned address. 12.
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USB Device Controller 14. When the host executes the STATUS OUT stage (zero-length OUT), the UDC sets the UDDCS0[OPR] bit, which causes an interrupt. 15. Software enters the ISR routine and determines that the UDCCS0[OPR] bit is set, the UDCCS0[SA] bit is clear, and its internal state machine is EP0_END_XFER. Software clears the UDCCS0[OPR] bit and transfers its internal state machine to EP0_IDLE. 16. Software clears the UDC interrupt bit and returns from the interrupt service routine.
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USB Device Controller 16. Software clears the UDC interrupt bit and returns from the interrupt service routine. If the host sends another SETUP command during these steps, the software must terminate the first SETUP command and start the new command. 12.5.3 Case 3: EP0 Control Write With or Without a Premature Status Stage 1. When software starts, it initializes a software state machine to EP0_IDLE. The software state machine is used to track stages when software communicates with the host PC. 2.
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USB Device Controller the wrong amount of data was sent, software cleans up any buffer pointers and disregards the received data. 20. Software changes its internal state machine to EP0_IDLE. 21. Software clears the UDC interrupt bit and returns from the interrupt service routine. If the host sends another SETUP command during these steps, the software must terminate the first SETUP command and start the new command. 12.5.4 Case 4: EP0 No Data Command 1.
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USB Device Controller 1. During the SETUP VENDOR command, software enables the DMA engine and masks the EP1 interrupt. The DMA start address must be aligned on a 16-byte boundary. a. If the packet size is 64 bytes, software transfers the all the data in one DMA descriptor and sets the UDCCS1[TSP] bit in the second DMA descriptor. b.
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USB Device Controller 2. The host PC sends a BULK-OUT. 3. The DMA engine reads data from the EP2 data FIFO (UDDR2). 4. Steps 2 and 3 repeat until all the data has been read from the host. 5. If the software receives an EP2 interrupt it completes the following process: a. If UDCCS2[RNE] is clear and UDCCS2[RSP] is set, the data packet was a zero-length packet. b.
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USB Device Controller 1. During the SETUP VENDOR command, software enables the DMA engine and masks the EP3 interrupt. The DMA start address must be aligned on a 16-byte boundary. a. If the packet size is 256 bytes, software transfers the all the data in one DMA descriptor. b. If the packet size is less than 256 bytes, software sets up a string of descriptors in which the odd numbered descriptors point to the data and the even numbered descriptors are writes to the UDCCS1[TSP] bit. 2.
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USB Device Controller When software receives a SETUP VENDOR command to set up an EP4 ISOCHRONOUS OUT transaction, it may take one of three courses of action, as appropriate for the chosen operating model: • Configure the DMA engine and disable the EP4 interrupt to allow the DMA engine to handle the transaction. • Enable the EP4 interrupt to allow the Megacell to directly handle the transaction. • Enable the SOF interrupt to handle the transaction on a frame count basis. 12.5.8.
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USB Device Controller 6. Return from interrupt. 7. Steps 2 through 6 repeat until all the data has been read from the host. 12.5.8.3 Software Enables the SOF Interrupt If software enables the SOF interrupt to handle the transaction on a frame count basis: 1. Software disables the UDCCS4 Interrupt by setting UICR0[IM4] to a 1 and enables the SOF interrupt in the UFNHR register by setting UFNHR[SIM] to a 0. 2. When the host PC sends an SOF, the UDC sets the UFNHR[SIR] bit, which causes an SOF interrupt. 3.
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USB Device Controller b. If UDCCR[UDA] is a 1, there is currently no USB reset on the bus and software enables future reset interrupts by clearing the UDCCR[REM] bit. 3. Return from interrupt. 4. The host either asserts a USB reset or negates a USB reset. 5. The UDC generates a Reset Interrupt. 6. Software determines that the UDCCR[RSTIR] bit is set and clears the interrupt by writing a 1 to the UDCCR[RSTIR] bit. Software then examines the UDCCR[UDA] bit to determine the type of reset that took place: a.
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USB Device Controller address for the 16 x 8 data FIFO that can be used to transmit and receive data. Endpoint 0 also has a write count register that is used to determine the number of bytes the USB host controller has sent to Endpoint 0. 12.6.1 UDC Control Register (UDCCR) UDCCR, shown in Table 12-12, contains seven control bits: one to enable the UDC, one to show activity, and five to show status and associated control functions. Table 12-12.
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USB Device Controller 12.6.1.2 UDC Active (UDA) This read-only bit can be read to determine if the UDC is currently active or in a USB reset. This bit is only valid when the UDC is enabled. A zero indicates that the UDC is currently receiving a USB reset from the host. A one indicates that the UDC is currently involved in a transaction. 12.6.1.
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USB Device Controller 12.6.2 UDC Control Function Register (UDCCFR) The UDC Control Function register (UDCCFR) contains 1 mode bit and 1 enable bit that lets software delay sending back an ACK response to SET_CONFIG or SET_INTERFACE commands from the host. The remaining bits are reserved and should not be written. Table 12-13.
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USB Device Controller 12.6.3 UDC Endpoint 0 Control/Status Register (UDCCS0) UDCCS0, shown in Table 12-14, contains seven bits that are used to operate endpoint zero, the control endpoint. Table 12-14. UDCCS0 Bit Definitions x x x x x x x x x x x x x x x x x Bits Name 0 OPR 1 IPR IN packet ready (always read 0/write 1 to set). 1 = IN packet ready. 2 FTF Flush Tx FIFO (always read 0/write 1 to set) 1 = Flush the contents of Tx FIFO.
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USB Device Controller When software enables the status stage for Vendor/Class commands and control data commands such as GET_DESCRIPTOR, GET_CONFIGURATION, GET_INTERFACE, GET_STATUS, and SET_DECSCRIPTOR, software must also set IPR. The data in the Transmit FIFO must be transmitted and the interrupt must be processed before the IPR is set for the status stage.
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USB Device Controller 12.6.4 UDC Endpoint x Control/Status Register (UDCCS1/6/11) UDCCS1/6/11, shown in Table 12-15, contains 6 bits that are used to operate endpoint(x), a Bulk IN endpoint). Table 12-15.
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USB Device Controller Setting this bit does not prevent the UDC from transmitting the next buffer. The UDC issues NAK handshakes to all IN tokens if this bit is set and neither buffer has been triggered by writing 64-bytes or setting UDCCSx[TSP]. When DMA loads the transmit buffers, the interrupt generated by UDCCSx[TPC] can be masked to allow data to be transmitted without core intervention. 12.6.4.3 Flush Tx FIFO (FTF) The Flush Tx FIFO bit triggers a reset for the endpoint's transmit FIFO.
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USB Device Controller 12.6.5 UDC Endpoint x Control/Status Register (UDCCS2/7/12) UDCCS2/7/12, shown in Table 12-16, contains 7 bits that are used to operate endpoint x, a Bulk OUT endpoint. Table 12-16.
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USB Device Controller exception is RNE which will get set with RPC but will clear itself once the active FIFO is empty. After clearing RPC, the next buffer will become active and the status bits will be updated accordingly, including RPC. The UDCCSx[RPC] bit is cleared by writing a 1 to it. The UDC issues NAK handshakes to all OUT tokens while this bit is set and both buffers have unread data. 12.6.5.3 Bit 2 Reserved Bit 2 is reserved for future use. 12.6.5.
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USB Device Controller These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits. 12.6.6 UDC Endpoint x Control/Status Register (UDCCS3/8/13) USCCS3/8/13, shown in Table 12-17, contains 4 bits that are used to operate endpoint(x), an Isochronous IN endpoint. Table 12-17.
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USB Device Controller When DMA is used to load the transmit buffers, the interrupt generated by UDCCSx[TPC] can be masked to allow data to be transmitted without core intervention. 12.6.6.3 Flush Tx FIFO (FTF) The Flush Tx FIFO bit triggers a reset for the endpoint's transmit FIFO. The Flush Tx FIFO bit is set when software writes a 1 to it or when the host performs a SET_CONFIGURATION or SET_INTERFACE. The bit’s read value is zero. 12.6.6.
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USB Device Controller Table 12-18.
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USB Device Controller 12.6.7.4 DMA Enable (DME) The DMA enable is used by the UDC to control the timing of the data received interrupt. If the bit is set, the interrupt is asserted when the end of packet is received and the receive FIFO has less than 32 bytes of data in it. If the bit is not set, the interrupt is asserted when the end of packet is received and all of the received data is still in the receive FIFO. 12.6.7.5 Bits 5:4 Reserved Bits 5:4 are reserved for future use. 12.6.7.
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USB Device Controller Table 12-19. UDCCS5/10/15 Bit Definitions (Sheet 2 of 2) UDCCS5 UDCCS5 UDCCS15 x x x x x x x x x x x x x x x x x Bits Name 5 FST Force STALL (read/write). 1 = Issue STALL handshakes to IN tokens. 4 SST Sent STALL (read/write 1 to clear). 1 = STALL handshake was sent. 3 TUR Transmit FIFO underrun (read/write 1 to clear) 1 = Transmit FIFO experienced an underrun.
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USB Device Controller 12.6.8.4 Transmit Underrun (TUR) The transmit underrun bit is be set if the transmit FIFO experiences an underrun. When the UDC experiences an underrun, NAK handshakes are sent to the host. UDCCSx[TUR] does not generate an interrupt and is for status only. UDCCSx[TUR] is cleared by writing a 1 to it. 12.6.8.5 Sent STALL (SST) The sent stall bit is set by the UDC in response to FST successfully forcing a user induced STALL on the USB bus.
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USB Device Controller Table 12-20.
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USB Device Controller 12.6.10 UDC Interrupt Control Register 1 (UICR1) UICR1, shown in Table 12-21, contains 8 control bits to enable/disable interrupt service requests from endpoints 8 - 15. The UICR1 bits are reset to 1 so interrupts are not generated on initial system reset. Table 12-21.
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USB Device Controller 12.6.11 UDC Status/Interrupt Register 0 (USIR0) USIR0, shown in Table 12-22, and USIR1, shown in Table 12-23, contain bits that are used to generate the UDC’s interrupt request. Each bit in the UDC status/interrupt registers is logically ORed together to produce one interrupt request. When the ISR for the UDC is executed, it must read the UDC status/interrupt register to determine why the interrupt occurred. USIRx is level sensitive.
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USB Device Controller 12.6.11.3 Endpoint 2 Interrupt Request (IR2) The interrupt request bit is set if the IM2 bit in the UDC interrupt control register is cleared and the OUT packet ready bit (RPC) in the UDC endpoint 2 control/status register is set. The IR2 bit is cleared by writing a 1 to it. 12.6.11.
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USB Device Controller 12.6.12 UDC Status/Interrupt Register 1 (USIR1) Table 12-23. USIR1 Bit Definitions x x x x x x x x x x x x x x x x x x x x x Bits Name 31:8 — 7 IR15 Interrupt Request Endpoint 15 (read/write 1 to clear) 1 = Endpoint 15 needs service. 6 IR14 Interrupt Request Endpoint 14 (read/write 1 to clear) 1 = Endpoint 14 needs service. 5 IR13 Interrupt Request Endpoint 13 (read/write 1 to clear) 1 = Endpoint 13 needs service.
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USB Device Controller 12.6.12.4 Endpoint 11 Interrupt Request (IR11) The interrupt request bit is set if the IM11 bit in the UDC interrupt control register is cleared and the IN packet complete (TPC) in UDC endpoint 11 control/status register is set. The IR11 bit is cleared by writing a 1 to it. 12.6.12.
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USB Device Controller Table 12-24. UFNHR Bit Definitions USB Device Controller Reset x x x x x x x Bits Name 31:8 — x x x x x x x x x x x x x x x x x 0 6 5 4 3 2 1 0 IPE4 reserved 7 IPE9 8 SIM 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 IPE14 Bit UFNHR SIR 0x 4060_0060 3-Bit Frame Number MSB 1 0 0 0 0 0 0 Description reserved SOF Interrupt Request (read/write 1 to clear) 1 = SOF has been received.
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USB Device Controller 12.6.13.4 Isochronous Packet Error Endpoint 14 (IPE14) The isochronous packet error for Endpoint 14 is set if Endpoint 14 is loaded with a data packet that is corrupted. This status bit is used in the interrupt generation of endpoint 14. To maintain synchronization, software must monitor this bit when it services the SOF interrupt and reads the frame number. This bit is not set if the token packet is corrupted or if the sync or PID fields of the data packet are corrupted. 12.6.13.
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USB Device Controller Table 12-26. UBCR2/4/7/9/12/14 Bit Definitions UBCR2 UBCR4 UBCR7 UBCR9 UBCR12 UBCR14 0x 4060_0068 0x 4060_006C 0x 4060_0070 0x 4060_0074 0x 4060_0078 0x 4060_007C Bit USB Device Controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 reserved Reset x x x x x x x x x x x x x 4 3 2 1 0 0 0 0 BC x x x x x x x x x x x 0 0 0 0 0 Bits Name 31:8 — reserved 7:0 BC Byte Count (read-only).
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USB Device Controller Table 12-27. UDDR0 Bit Definitions 0x 4060_0080 Bit UDDR0 USB Device Controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 x x x x x x x Bits Name 31:8 — x x x x x x 6 5 4 3 2 1 0 Bottom of Endpoint 0 FIFO (for Reads) Top of Endpoint 0 FIFO (for Writes) reserved Reset 7 x x x x x x x x x x x 0 0 0 0 0 0 0 0 Description reserved Top/bottom of endpoint 0 FIFO data.
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USB Device Controller These are read-only registers. Ignore reads from reserved bits. Table 12-29. UDDR2/7/12 Bit Definitions UDDR2 UDDR7 UDDR12 0x 4060_0180 0x 4060_0680 0x 4060_0B80 Bit USB Device Controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 reserved Reset x x x x x x x Bits Name 31:8 — 7:0 DATA 12.6.
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USB Device Controller Table 12-31. UDDR4/9/14 Bit Definitions UDDR4 UDDR9 UDDR14 0x 4060_0400 0x 4060_0900 0x 4060_0E00 Bit USB Device Controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 reserved Reset x x x x x Bits x x x x x x x — 7:0 DATA 4 3 2 1 0 0 0 8-bit Data x x x x x Name 31:8 12.6.
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USB Device Controller Table 12-33.
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USB Device Controller Table 12-33.
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AC’97 Controller Unit 13.1 13 Overview The AC’97 Controller Unit (ACUNIT) of the PXA255 processor supports the AC’97 revision 2.0 features listed in Section 13.2. The ACUNIT also supports audio controller link (AC-link). AClink is a serial interface for transferring digital audio, modem, mic-in, CODEC register control, and status information. The AC’97 CODEC sends the digitized audio samples that the ACUNIT stores in memory.
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AC’97 Controller Unit 13.3 Signal Description The AC’97 signals form the AC-link, which is a point-to-point synchronous serial interconnect that supports full-duplex data transfers. All digital audio streams, Modem line CODEC streams, and command/status information are communicated over the AC-link. The AC-link uses General Purpose I/Os (GPIOs). Software must reconfigure the GPIOs to use them as the AC-link. The AClink pins are listed and described in Table 13-1. Table 13-1.
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AC’97 Controller Unit Figure 13-1. Data Transfer Through the AC-link AC’97 Controller Unit (ACUNIT) AC-link AC’97 Primary CODEC nACRESET SDATA_OUT SYNC (48 kHz) SDATA_IN_0 SDATA_IN_1 BITCLK (12.288 MHz) AC’97 Secondary CODEC 13.4 AC-link Digital Serial Interface Protocol Each AC’97 CODEC incorporates a five-pin digital serial interface that links it to the ACUNIT. AC-link is a full-duplex, fixed-clock, PCM digital stream.
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AC’97 Controller Unit Table 13-2. Supported Data Stream Formats (Sheet 2 of 2) Channel Slots Comments Dedicated Microphone Input One input slot Dedicated microphone input stream in support of stereo AEC and other voice applications. I/O Control One output slot One slot dedicated to GPOs on the modem CODEC. One input slot One slot dedicated to status from GPIs on the modem CODEC. Data is returned on every frame.
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AC’97 Controller Unit Figure 13-3. AC-link Audio Output Frame Tag Phase Data Phase 20.8uS (48 KHz) 12.288 MHz SYNC 81.4 nS BIT_CLK Valid Frame SDATA_OUT End of previous Audio Frame slot(1) slot(2) slot(12) "0" 19 codec ID codec ID Time Slot "Valid" Bits ("1" = time slot contains valid PCM data) 0 Slot 1 19 0 Slot 2 19 0 Slot 3 19 0 Slot 12 A new audio output frame begins with a low-to-high SYNC transition synchronous to BITCLK’s rising edge.
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AC’97 Controller Unit 13.4.1.1 Slot 0: Tag Phase In slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) that flags the validity for the entire audio frame. If the valid frame bit is a 1, the current audio frame contains at least one slot time of valid data. The next 12 bit positions sampled by AC’97 indicate which of the corresponding 12 time slots contain valid data.
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AC’97 Controller Unit Table 13-3. Slot 1 Bit Definitions Bit Name Description Bit(19) RW 1 = read, 0 = write Bit(18:12) IDX Code register index Bit(11:0) reserved Stuff with 0s Only one I/O cycle can be pending across the AC-link at any time. The ACUNIT uses write and read posting on I/O accesses across the link. For example, read data from a CODEC register is not sent over the AC-link (Slot 2 of incoming stream) within the same frame that the read request is sent.
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AC’97 Controller Unit 13.4.1.5 Slot 4: PCM Playback Right Channel Slot 4 is the composite digital audio right playback stream. If the playback stream contains an audio sample with a resolution that is less than 20 bits, the ACUNIT fills all trailing non-valid bit positions with zeroes. 13.4.1.6 Slot 5: Modem Line CODEC Slot 5 contains the MSB justified modem DAC input data if the modem line CODEC is supported. The optional modem DAC input resolution can be implemented as 16, 18, or 20 bits.
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AC’97 Controller Unit Figure 13-5. AC’97 Input Frame Tag Phase Data Phase 20.8uS (48 KHz) 12.288 MHz SYNC 81.4 nS BIT_CLK Codec Ready SDATA_IN End of previous Audio Frame slot(1) slot(2) slot(12) "0" "0" "0" Time Slot "Valid" Bits ("1" = time slot contains valid PCM data) 19 0 19 Slot 1 0 Slot 2 19 0 Slot 3 19 0 Slot 12 A new audio input frame begins when SYNC transitions from low to high. The low to high transition is synchronous to BITCLK’s rising edge.
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AC’97 Controller Unit CODEC Ready, sent by the CODEC on its data out stream in bit 15 of Slot 0, is not expected to change during normal operation. The AC’97 Specification revision 2.0 requires that a CODEC only change its CODEC Ready status in response to a power down (PR) state change issued by the ACUNIT. The ACUNIT’s hardware by itself does not monitor the CODEC Ready for the purpose of sending or receiving data.
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AC’97 Controller Unit Table 13-5. Input Slot 1 Bit Definitions (Sheet 2 of 2) 4 Slot 10 request: NA 3 Slot 11 request: NA 2 Slot 12 request: NA 1,0 reserved (Filled with zero) SLOTREQ bits are independent of the Control Register Index bits. Note: 13.4.2.3 Slot requests for Slot 3 and Slot 4 are always set or cleared in tandem (both are set or both are cleared). Slot 2: Status Data Port Slot 2 delivers 16-bit control register read data. Table 13-6. Input Slot 2 Bit Definitions Bit Note: 13.4.
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AC’97 Controller Unit The ACUNIT only supports a 16-bit resolution from the microphone. 13.4.2.8 Slots 7-11: Reserved Slots 7-11 are reserved for future use. The ACUINT ignores them. 13.4.2.9 Slot 12: I/O Status GPIOs which are configured as inputs return their status in Slot 12 of every frame. Only the 16 MSBs are used to return GPIO status. Bit 0 in the LSBs indicates a GPI Input Interrupt event. See the AC’97 revision 2.0 spec for more information.
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AC’97 Controller Unit The ACUNIT transmits the write to the Powerdown Register (0x26) over the AC-link. Set up the ACUNIT so that it does not transmit data in Slots 3-12 when it writes 0x1000 to the PR4 bit of the Powerdown Register. AC’97 revision 2.0 does not require the CODEC to process other data when it receives a power down request. When the CODEC receives the power down request, it immediately transitions BITCLK and SDATA_IN to a logic low level. 13.5.2 Waking up the AC-link 13.5.2.
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AC’97 Controller Unit 13.5.2.2 Wake Up Triggered by the ACUNIT AC-link protocol provides for a cold AC’97 reset and a warm AC’97 reset. The current powerdown state ultimately dictates which AC’97 reset is used. Registers must stay in the same state during all power-down modes unless a cold AC’97 reset is performed. In a cold AC’97 reset, the AC’97 registers are initialized to their default values.
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AC’97 Controller Unit Receive FIFO entries are read through the PCDR, the MODR, or the Mic-in Data Register (MCDR). Note: After it is enabled, the ACUNIT requests the DMA to fill the transmit FIFO. Note: The ACUNIT registers do not store the status of DMA requests or information regarding the number of data samples in each FIFO. As a result, programmed I/O must not be used in place of DMA requests for data transfers. Only the DMA can access the FIFOs.
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AC’97 Controller Unit ACUNIT does not set the CODEC-ready bit, GCR[PCRDY] for the Primary CODEC or GCR[SCRDY] for the Secondary CODEC.
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AC’97 Controller Unit 13.6.2 Trailing bytes Trailing bytes in the transmit and receive FIFOs are handled as follows: If the transmit buffers do not have 32-byte resolution, the trailing bytes in the Transmit FIFO are not transmitted. A transmit buffer must be padded with zeroes if it is smaller than a multiple of 32 bytes. Regardless of burst size, the DMA descriptor length must be a multiple of 32 bytes to prevent audio artifacts from being introduced onto the AC-link.
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AC’97 Controller Unit All data transfers across the AC-link are synchronized to SYNC’s rising edge. The ACUNIT divides the BITCLK by 256 to generate the SYNC signal. This calculation yields a 48 kHz SYNC signal, and its period defines a frame. Data is transitioned on AC-link on every BITCLK rising edge and subsequently sampled on AC-link’s receiving side on each following BITCLK falling edge. For a timing diagram see Figure 13-3.
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AC’97 Controller Unit 13.8.2 Interrupts The following status bits interrupt the processor when the interrupts are enabled: • • • • • • Mic-in FIFO error: Mic-in Receive FIFO’s over-run or under-run error. Modem-in FIFO error: Modem Receive FIFO’s over-run or under-run error. PCM-in FIFO error: Audio Receive FIFO’s over-run or under-run error. Modem-out FIFO error: Modem Transmit FIFO’s over-run or under-run error. PCM-out FIFO error: Audio Transmit FIFO’s over-run or under-run error.
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AC’97 Controller Unit Channel specific data registers are for FIFO accesses and the PCM, Modem, and Mic-in FIFOs each have a register. A write access to one of these registers updates the written data in the corresponding Transmit FIFO. A read access to one of these registers flushes out an entry from the corresponding Receive FIFO. Note: Register tables show organization and individual bit definitions. All reserved bits are read as unknown values and must be written with a 0.
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AC’97 Controller Unit Table 13-7.
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AC’97 Controller Unit Table 13-8.
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AC’97 Controller Unit Table 13-8.
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AC’97 Controller Unit Table 13-9.
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AC’97 Controller Unit 13.8.3.5 PCM-Out Status Register (POSR) This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 13-11.
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AC’97 Controller Unit 13.8.3.7 CODEC Access Register (CAR) This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 13-13.
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AC’97 Controller Unit Figure 13-9. PCM Transmit and Receive Operation Transmit Data Processor/DMA Write Receive Data Processor/DMA Read RxEntry15 TxEntry15 PCDR Register PCM Transmit FIFO 31 TxEntry3 RxEntry3 RxFIFO Read TxFIFO Written TxEntry2 PCM Receive FIFO 0 RxEntry2 RxEntry1 TxEntry1 Right 31 13.8.3.9 TxEntry0 Left 16 15 Right 31 0 RxEntry0 Left 16 15 0 Mic-In Control Register (MCCR) This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
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AC’97 Controller Unit Table 13-16. MCSR Bit Definitions AC’97 Controller Unit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 0 0 0 0 reserved Reset 0 0 0 0 0 0 0 0 Bits Name 31:5 — 0 0 0 0 0 0 0 4 3 2 0 0 FIFOE Bit MCSR Register 0 0 0 0 0 0 0 0 0 1 0 0 0 reserved Physical Address 4050_0018 Description reserved FIFO error (FIFOE) 4 FIFOE 3:0 — 0 = No Receive FIFO error has occurred. 1 = A receive FIFO error occurred.
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AC’97 Controller Unit Figure 13-10. Mic-in Receive-Only Operation Receive Data Processor/DMA Read RxEntry15 MCDR Register 0x0000 Mic-in Receive FIFO 31 0 16 15 RxFIFO Read RxEntry3 RxEntry2 RxEntry1 RxEntry0 15 13.8.3.12 0 Modem-Out Control Register (MOCR) This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 13-18.
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AC’97 Controller Unit Table 13-19. MICR Bit Definitions AC’97 Controller Unit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 reserved Reset 0 0 0 0 0 0 0 Bits Name 31:4 — 0 0 0 0 0 0 0 0 3 2 FEIE Bit MICR Register 0 0 0 0 0 0 0 0 0 1 0 reserved Physical Address 4050_0108 0 0 0 Description reserved FIFO Error Interrupt Enable (FEIE) 3 Controls whether a receive FIFO error causes an interrupt.
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AC’97 Controller Unit Table 13-21. MISR Bit Definitions AC’97 Controller Unit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 0 0 0 0 reserved Reset 0 0 0 0 0 0 0 0 Bits Name 31:5 — 0 0 0 0 0 0 0 4 3 2 0 0 FIFOE Bit MISR Register 0 0 0 0 0 0 0 0 0 1 0 0 0 reserved Physical Address 4050_0118 Description reserved FIFO error (FIFOE) 4 FIFOE 3:0 — 0 = No Receive FIFO error has occurred. 1 = A receive FIFO error occurred.
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AC’97 Controller Unit Figure 13-11. Modem Transmit and Receive Operation Transmit data Processor/DMA Write RxEntry15 TxEntry15 0x0000 Modem Transmit FIFO 15 13.8.3.17 Receive Data Processor DMA Read 31 MODR Register 1615 Modem Receive FIFO 0 TxEntry3 RxEntry3 TxEntry2 RxEntry2 TxEntry1 RxEntry1 TxEntry0 RxEntry0 15 0 0 Accessing CODEC Registers Each CODEC has up to sixty-four 16-bit registers that are addressable internal to the CODEC at half-word boundaries (16-bit boundaries).
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AC’97 Controller Unit Table 13-23.
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AC’97 Controller Unit Table 13-23.
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AC’97 Controller Unit 13.9 AC’97 Register Summary All AC’97 registers are word-addressable (32 bits wide) and increment in units of 0x00004. The registers in the CODEC are half-word addressable (16 bits wide), and increment in units of 0x00002. These register sets are mapped in the address range of 0x4050_000 through 0x405F_FFFF. Table 13-24.
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AC’97 Controller Unit 13-36 Intel® PXA255 Processor Developer’s Manual
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Inter-Integrated-Circuit Sound (I2S) Controller 14 I2S is a protocol for digital stereo audio. The I2S Controller (I2SC) functional block for the PXA255 processor controls the I2S link (I2SLINK), which is a low-power four-pin serial interface for stereo audio. The I2S interface and the Audio CODEC ‘97 (AC’97) interface may not be used at the same time. 14.
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Inter-Integrated-Circuit Sound (I2S) Controller 14.2 Signal Descriptions SYSCLK is the clock on which all other clocks in the I2S unit are based. SYSCLK generates a frequency between approximately 2 MHz and 12.2 MHz by dividing down the PLL clock with a programmable divisor. This frequency is always 256 times the audio sampling frequency. SYSCLK is driven out of the processor system only if BITCLK is configured as an output.
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Inter-Integrated-Circuit Sound (I2S) Controller 2. Program SYSUNIT’s GPIO Alternate Function Select Register (GAFR). See Section 4.1.3.6, “GPIO Alternate Function Register (GAFR0_L, GAFR0_U, GAFR1_L, GAFR1_U, GAFR2_L, GAFR2_U)” on page 4-16 for details regarding the GAFR. To configure SYNC and SDATA_OUT as outputs, follow these steps: 1. Program SYSUNIT’s GPIO Direction Register (GPDR). See Section 4.1.3.2, “GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)” on page 4-8 for details regarding the GPDR. 2.
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Inter-Integrated-Circuit Sound (I2S) Controller 2. Choose between Normal I2S or MSB-Justified modes of operation. This can be done by programming bit 0 of Serial Audio Controller I2S/MSB-Justified Control Register (SACR1). For further details, see Section 14.6.2. 3. Optional: Programmed I/O may be used for priming the Transmit FIFO with a few samples (ranging from 1 to 16). If the I2SLINK is enabled with an empty Transmit FIFO, a Transmit Under-run error bit will be set in the Status register.
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Inter-Integrated-Circuit Sound (I2S) Controller Asserting the DREC bit in SACR1 has the following effects: 1. I2SLINK recording activity is disabled. The frame or data sample, in the midst of which the recording is disabled, could have invalid data (some data bits will be over-written with zeros). To avoid this, disable record only after the transfer of valid data. 2. Receive FIFO pointers are reset to zero. 3. Receive FIFO fill-level is reset to zero. 4.
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Inter-Integrated-Circuit Sound (I2S) Controller The BITCLK, as shown in Table 14-2, is different for different sampling frequencies. If the BITCLK is chosen as an output, the Audio Clock Divider Register divides the 147.46MHz PLL clock to generate the SYSCLK. The SYSCLK is further divided by four to generate the BITCLK. The sampling frequency is the frequency of the SYNC signal, which is generated by dividing the BITCLK by 64. See Section 14.6.4, for further details about the register.
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Inter-Integrated-Circuit Sound (I2S) Controller Figure 14-1 and Figure 14-2 provide timing diagrams that show formats for I2S and MSB-justified modes of operations. Data is transmitted and received in frames of 64 BITCLK cycles. Each frame consists of a Left sample and a Right sample. Each frame holds 16-bits of valid sample data (shown in the figures) and 16-bits of padded zeros (not shown in the figures). The transmit and receive FIFOs only hold valid sample data (not padded zero data).
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Inter-Integrated-Circuit Sound (I2S) Controller 14.6 Registers The I2S Controller registers are all 32-bit addressable, ranging from 0x4040_0000 through 0x404F_FFFF. The I2S Controller has the following types of registers: • Control registers are used to program common control, alternate mode specific control. • The Data Register is used for Transmit and Receive FIFO accesses.
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Inter-Integrated-Circuit Sound (I2S) Controller Table 14-3.
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Inter-Integrated-Circuit Sound (I2S) Controller Table 14-4. FIFO Write/Read table EFWR STRF Description Normal CPU/DMA Write/Read condition: • A write access to the Data Register writes a Transmit FIFO entry. 0 x • A read access to the Data Register reads out a Receive FIFO entry. • I2SLINK reads from the Transmit FIFO and writes to the Receive FIFO. CPU or DMA only writes and reads Transmit FIFO: • A write access to the Data Register writes a Transmit FIFO entry.
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Inter-Integrated-Circuit Sound (I2S) Controller Table 14-6.
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Inter-Integrated-Circuit Sound (I2S) Controller Table 14-7.
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Inter-Integrated-Circuit Sound (I2S) Controller The reset value, 0x0000001A, defaults to a sampling frequency of 22.05 kHz. Note: Setting this register to values other than those shown in Section 14.2 is not allowed and will cause unpredictable activity. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 14-8.
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Inter-Integrated-Circuit Sound (I2S) Controller 14.6.6 Serial Audio Interrupt Mask Register (SAIMR) Writing a one to the corresponding bit position in the SAIMR, shown in Table 14-10, enables the corresponding interrupt signal. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 14-10.
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Inter-Integrated-Circuit Sound (I2S) Controller Figure 14-3. Transmit and Receive FIFO Accesses Through the SADR Transmit Data Processor/DMA Write Receive Data Processor/DMA Read RxEntry15 TxEntry15 SADR Register PCM Transmit FIFO 31 TxEntry3 TxFIFO Written TxEntry2 PCM Receive FIFO 0 RxEntry3 RxFIFO Read RxEntry2 RxEntry1 TxEntry1 TxEntry0 Right Left 31 16 15 14.
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Inter-Integrated-Circuit Sound (I2S) Controller Table 14-12.
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15 MultiMediaCard Controller 15.1 Overview The PXA255 processor MultiMediaCard (MMC) controller acts as a link between the software used to access the processor and the MMC stack (a set of memory cards). The MMC controller is designed to support the MMC system, a low-cost data storage and communications system. A detailed description of the MMC system is available through the MMC Association’s web site at www.mmca.org.
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MultiMediaCard Controller The MMC bus connects the card stack to the controller. The software and controller can turn the MMC clock on and off. The card stack and the controller communicate serially through the command and data lines and implement a message-based protocol. The messages consist of the following tokens: • Command: a 6-byte command token starts an operation. The command set includes card initialization, card register reads and writes, data transfers, etc.
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MultiMediaCard Controller the bidirectional MMDAT signal. A typical MMC mode command timing diagram with and without a response is shown in Figure 15-2 while Figure 15-3 shows a typical MMC mode timing diagram for a sequential read or write . Figure 15-2. MMC Mode Operation Without Data Token from host to card(s) from host to card Command MMCMD from card to host Command Response MMDAT Operation (No Response) Operation (No Data) Figure 15-3.
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MultiMediaCard Controller Figure 15-4. SPI Mode Operation Without Data Token from host to card MMCMD Command MMDAT from card to host from host to card from card to host Command Response Response Busy Figure 15-5. SPI Mode Read Operation from host to MMCMD from card to data from card to Next Command MMDAT Command Response Data Block CRC Figure 15-6.
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MultiMediaCard Controller The MMC controller is the interface between the software and the MMC bus. It is responsible for the timing and protocol between the software and the MMC bus. It consists of control and status registers, a 16-bit response FIFO that is eight entries deep, two 8-bit receive data FIFOs that are 32 entries deep, and two 8-bit transmit FIFOs that are 32 entries deep. The registers and FIFOs are accessible by the software.
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MultiMediaCard Controller 15.2.1 Signal Description The MMC controller signals are MMCLK, MMCMD, MMDAT, MMCCS0, and MMCCS1. Table 15-4 describes each signal’s function. Table 15-4.
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MultiMediaCard Controller 15.2.4.1 MMC Mode In MMC mode, the MMCMD and MMDAT signals are bidirectional and require external pullups. The command and response tokens are sent and received via the MMCMD signal and data is read and written via the MMDAT signal. After an MMC card is powered on, it is assigned a default relative card address (RCA) of 0x0001. The software assigns different addresses to each card during the initialization sequence described in Section 15.2.3.
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MultiMediaCard Controller 15.2.4.2 SPI Mode SPI mode is an optional secondary communication protocol. In SPI mode, the MMCMD and MMDAT lines are unidirectional and only single block data transfers are allowed. The MMCMD signal is an output from the controller and sends the command token and write data to the MMC card. The MMDAT signal is an input to the controller and receives the response token and read data from the MMC card.
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MultiMediaCard Controller 15.2.7 Clock Control Both the MMC controller and the software can control the MMC bus clock (MMCLK) by turning it on and off. This helps to control the data flow to prevent under runs and overflows and also conserves power. The software can also change the frequency at any time to achieve the maximum data transfer rate specified for a card’s identification frequency. The MMC controller has an internal frequency generator that may start, stop, and divide the MMC bus clock.
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MultiMediaCard Controller 15.2.8 Data FIFOs The controller FIFOs for the response tokens, received data, and transmitted data are MMC_RES, MMC_RXFIFO, and MMC_TXFIFO, respectively. These FIFOs are accessible by the software and are described in the following paragraphs. 15.2.8.1 Response Data FIFO (MMC_RES) The response FIFO, MMC_RES, contains the response received from an MMC card after a command is sent from the controller. MMC_RES is a read only, 16-bit, and 8-entry deep FIFO.
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MultiMediaCard Controller If the DMA is used, it must be programmed to do 1-byte reads of 32-byte bursts. The last read can be less than a 32-byte burst. Some examples are: • Receive 96 bytes of data: Read 32 bytes three times. For the DMA, use three descriptors of 32 bytes and 32-byte bursts. • Receive 98 bytes of data: Read 32 bytes three times, then read two more bytes.
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MultiMediaCard Controller When the DMA is used, it must be programmed to do 1-byte writes of 32-byte bursts. The last write can be less than a 32-byte burst. If the last write is less than 32 bytes, then the MMC_PRTBUF[BUF_PART_FULL] bit must be set. When the DMA is used, the last descriptor must be programmed to allow the DMA to set an interrupt after the data is written to the FIFO. After the interrupt occurs, the software must set the MMC_PRTBUF[BUF_PART_FULL] bit.
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MultiMediaCard Controller 15.3.1 Basic, No Data, Command and Response Sequence The MMC controller performs the basic MMC or SPI bus transaction. It formats the command from the command registers and generates and appends the 7-bit CRC if applicable. It then serially translates this to the MMCMD bus, collects the response data, and validates the response CRC. It also checks for response time-outs and card busy if applicable.
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MultiMediaCard Controller After completely reading or writing the data FIFOs, the software must wait for the appropriate interrupts. The status register, MMC_STAT, must be read to ensure that the transaction is complete and to check the status of the transaction. When using DMA request signals, the controller indicates to the DMA when a FIFO is ready for reading or writing. It is expected that all FIFO reads and writes will empty and fill the FIFO to which it is connected.
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MultiMediaCard Controller 15.3.2.2 Block Data Read In a single block data read, a block of data is read from a card. In a multiple block read, the controller performs multiple single block read data transfers on the MMC bus. After turning the clock on to start the command sequence, the software must program the DMA to empty the MMC_RXFIFO (read 32 bytes). The software will continue the process of emptying the FIFO until all of the data has been read from the FIFO.
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MultiMediaCard Controller In a stream data write, the following parameters must be specified: • The data transfer is a write. • The data transfer is in stream mode • The block length, if the block length is different from the previous block data transfer or this is the first time that the parameter is being specified. • The number of blocks to be transferred as 0xffff. 15.3.2.
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MultiMediaCard Controller 15.3.4 SPI Functionality The MMC controller can address up to two cards in SPI mode using the MMCCS[1:0] chip select signals. Once the software specifies which chip select to enable in the MMC_SPI register, the selected signal is driven active low at a falling edge of the MMC clock. The chip select remains asserted until software clears the chip select enable bit or selects another card. Note: The clock must be stopped before writing to any registers as described in Section 15.
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MultiMediaCard Controller 3. MMC_SPI[SPI_CS_ADDRESS] must be set to specify the card that the software wants to address. A 1 enables CS0 and a 0 enables CS1. Note: 15.4.4 When the card is in SPI mode, the only way to return to MMC mode is by toggling power to the card. No Data Command and Response Sequence For the basic no data transfer, command and response transaction, the software must: 1. Turn the clock off, as described in Section 15.4.1. 2. Write the command index in the MMC_CMD[CMD_INDEX] bits.
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MultiMediaCard Controller • Update the MMC_CMDAT register as: — Write 0x01 to MMC_CMDAT[RESPONSE_FORMAT] — Set the MMC_CMDAT[DATA_EN] bit. — Set the MMC_CMDAT[WRITE/READ] bit. — Clear the MMC_CMDAT[STREAM_BLOCK] bit. — Clear the MMC_CMDAT[BUSY] bit. — Clear the MMC_CMDAT[INIT] bit. • Turn the clock on. After it starts the clock, the software must perform these steps: 1. Wait for the response as described in Section 15.4.4. 2.
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MultiMediaCard Controller These registers must be set before the clock is started: • Update these MMC_CMDAT register bits: — Set the MMC_CMDAT[RESPONSE_FORMAT] bit. — Set the MMC_CMDAT[DATA_EN] bit. — Clear the MMC_CMDAT[WRITE/READ] bit. — Clear the MMC_CMDAT[STREAM_BLOCK] bit. — Clear the MMC_CMDAT[BUSY] bit. — Clear the MMC_CMDAT[INIT] bit. • Set MMC_NOB register to 0x0001. • Set MMC_BLKLEN register to the number of bytes per block. • Turn the clock on.
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MultiMediaCard Controller 15.4.10 Stream Write In a stream write command, the software must stop the clock and set the registers as described in Section 15.4.4. These registers must be set before the clock is started: • Set MMC_NOB register to ffffh. • Set MMC_BLKLEN register to the number of bytes per block. • Update MMC_CMDAT register as: — Write 0b01 to the MMC_CMDAT[RESPONSE_FORMAT]. — Set the MMC_CMDAT[DATA_EN] bit. — Set the MMC_CMDAT[WRITE/READ] bit. — Set the MMC_CMDAT[STREAM_BLOCK] bit.
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MultiMediaCard Controller • Set MMC_BLKLEN register to the number of bytes per block. • Update the MMC_CMDAT register as: — Write 0x01 to the MMC_CMDAT[RESPONSE_FORMAT]. — Set the MMC_CMDAT[DATA_EN] bit. — Clear the MMC_CMDAT[WRITE/READ] bit. — Set the MMC_CMDAT[STREAM_BLOCK] bit. — Clear the MMC_CMDAT[BUSY] bit. — Clear the MMC_CMDAT[INIT] bit. • Turn the clock on. After it turns the clock on, the software must perform these steps: 1. Wait for the response as described in Section 15.4.4. 2.
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MultiMediaCard Controller Table 15-5.
PAGE 526
MultiMediaCard Controller Table 15-6.
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MultiMediaCard Controller This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 15-7.
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MultiMediaCard Controller Table 15-8. MMC_SPI Bit Definitions (Sheet 2 of 2) 8 7 6 5 4 0 0 0 0 0 reserved Reset 0 0 0 0 0 Bits 0 0 0 0 0 0 0 0 0 0 0 0 0 Name 0 0 0 0 0 3 2 1 0 SPI_EN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 CRC_ON MultiMediaCard Controller SPI_CS_EN Bit MMC_SPI Register SPI_CS_ADDRESS Physical Address 0x4110_000c 0 0 0 0 Description SPI Mode Enable 0 SPI_EN 15.5.
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MultiMediaCard Controller Table 15-9.
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MultiMediaCard Controller 15.5.7 MMC_RDTO Register (MMC_RDTO) MMC_RDTO, shown in Table 15-11, determines the length of time that the controller waits after a command before it turns on the time-out error if data has not been received.
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MultiMediaCard Controller 15.5.8 MMC_BLKLEN Register (MMC_BLKLEN) MMC_BLKLEN, shown in Table 15-12, specifies the number of bytes in a block of data. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 15-12.
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MultiMediaCard Controller 15.5.10 MMC_PRTBUF Register (MMC_PRTBUF) MMC_PRTBUF, shown in Table 15-14, is used when MMC_TXFIFO is partially written. The FIFOs swap when either FIFO is full (32 bytes) or the MMC_PRTBUF register is set to a 1. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 15-14.
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MultiMediaCard Controller Table 15-15.
PAGE 534
MultiMediaCard Controller Table 15-16.
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MultiMediaCard Controller 15.5.13 MMC_CMD Register (MMC_CMD) MMC_CMD, shown in Table 15-17, specifies the command number. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 15-17.
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MultiMediaCard Controller Table 15-18.
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MultiMediaCard Controller Table 15-18. Command Index Values (Sheet 3 of 3) 15.5.
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MultiMediaCard Controller 15.5.16 MMC_RES FIFO MMC_RES FIFO, shown in Table 15-21, contains the response after a command. It is 16 bits wide by eight entries.The RES FIFO does not contain the 7-bit CRC for the response. The status for CRC checking and response time-out status is in the status register, MMC_STAT. The first half-word read from the response FIFO is the most significant half-word of the received response. This is a read-only register. Ignore reads from reserved bits. Table 15-21.
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MultiMediaCard Controller 15.5.18 MMC_TXFIFO FIFO MMC_TXFIFO, shown in Table 15-23, consists of two dual FIFOs, where each FIFO is eight bits wide by 32 entries deep. This FIFO holds the data to be written to a card. It is a write only FIFO to the software, and is written on boundaries eight bits wide. The eight bits of data are written on a 32bit APB and occupy the least significant byte lane (7:0). This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
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MultiMediaCard Controller Table 15-24.
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Network SSP Serial Port 16 This chapter describes the signal definitions and operation of the Intel® PXA255 Processor Network Synchronous Serial Protocol (NSSP) serial port. The NSSP is configured differently than the SSPC. 16.1 Overview The NSSP is a synchronous serial interface that connects to a variety of external analog-to-digital (A/D) converters, telecommunication CODECs, and many other devices that use serial protocols for data transfer.
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Network SSP Serial Port 16.3 Signal Description Table 16-1 lists the external signals between the SSP serial ports and external device. If the port is disabled, its pins are available for GPIO use. See Section 4.1, “General-Purpose I/O” for details on configuring pin direction and Section 4.2, “Interrupt Controller” for Interrupt capabilities. Table 16-1.
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Network SSP Serial Port The FIFOs can also be accessed by DMA bursts (in multiples of one, two or four bytes) depending upon the EDSS value. When SSCR0[EDSS] is set, DMA bursts must be in multiples of four bytes (the DMA must have the SSP configured as a 32-bit peripheral).When SSCR0[EDSS] is cleared, DMA bursts must be in multiples of one or two bytes (the DMA’s DCMD[WIDTH] register must be at least the SSP data size programmed into the SSCR0[EDSS] and SSCR0[DSS].
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Network SSP Serial Port • • • • SSPSCLK–Defines the bit rate at which serial data is driven onto and sampled from the port. SSPSFRM–Defines the boundaries of a basic data unit, comprised of multiple serial bits. SSPTXD–The serial data path for transmitted data, from system to peripheral. SSPRXD–The serial data path for received data, from peripheral to system. A data frame can contain from four to 32-bits, depending on the selected protocol. Serial data is transmitted most significant bit first.
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Network SSP Serial Port transmit data exist within the transmit FIFO. At other times, SSPSCLK holds in an inactive or idle state as defined by the protocol. 16.4.3.1 TI Synchronous Serial Protocol* Details When outgoing data in the SSP controller is ready to transmit, SSPSFRM asserts for one clock period. On the following clock, data to be transmitted is driven on SSPTXD one bit at a time, the most significant bit first. For receive data, the peripheral similarly drives data on the SSPRXD pin.
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Network SSP Serial Port Figure 16-2. Texas Instruments Synchronous Serial Frame* Protocol (single transfers) SSPSCLK SSPSFRM SSPTXD SSPRXD Undefined Bit[N] Bit[N-1] Bit[1] Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0] MSB 4 to 32 Bits Undefined LSB A9518-02 16.4.3.2 SPI Protocol Details The SPI protocol has four possible sub-modes, depending on the SSPSCLK edges selected for driving data and sampling received data and on the selection of the phase mode of SSPSCLK (see Section 16.4.3.2.
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Network SSP Serial Port Figure 16-3. Motorola SPI* Frame Protocol (multiple transfers) SSPSCLK SSPSFRM SSPTX Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0] Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0] SSPRX Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0] Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0] A9651-01 Note: When configured as either master or slave (to clock or frame) the SSP continues to drive SSPTXD with the last bit of data sent (the LSB). If SSCR0[SSE] is cleared, SSPTXD goes low.
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Network SSP Serial Port When SPH is set, SSPSCLK remains in its inactive or idle state (as determined by SSCR1[SPO]) for one-half cycle after SSPSFRM is asserted low at the beginning of a frame. SSPSCLK continues to transition for the remainder of the frame and is then held in its inactive state for one full SSPSCLK period before SSPSFRM is de-asserted high at the end of the frame.
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Network SSP Serial Port SSPRXD is undefined before the MSB and after the LSB is transmitted. For minimum power consumption, this pin must not float. Figure 16-6. Motorola SPI* Frame Protocols for SPO and SPH Programming (single transfers) SSPSCLK SSPSCLK SPO=0 SPO=1 SSPSFRM Bit[N] SSPTXD SSPRXD Undefined Bit[N] MSB Bit[N-1] Bit[1] Bit[N-1] Bit[1] 4 to 32 Bits Bit[0] Bit[0] End of Transfer Data State Undefined LSB A9520-02 Note: 16.4.3.
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Network SSP Serial Port Figure 16-7. National Semiconductor Microwire* Frame Protocol (multiple transfers) SSPSCLK SSPSFRM Bit[7] or Bit[15] SSPTX/RX Bit[0] SSPTX/RX Undefined Bit[N] Undefined Bit[1] Bit[0] Bit[0] Bit[N] Undefined A9653-01 Note: When configured master the SSP continues to drive SSPTXD with the last bit of data sent (the LSB) or it drives zero, depending on the status of SSPSP[ETDS]. If SSCR0[SSE] is cleared, SSPTXD goes low.
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Network SSP Serial Port clocks programmed in the field SSPSP[SFRMP]. The SSPSFRM remains asserted for the number of half-clocks programmed within SSPSP[SFRMWDTH]. Four to 32-bits can be transferred per frame. Once the LSB transfers, the SSPSCLK continues toggling based on the dummy stop field (SSPSP[DMYSTOP]).
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Network SSP Serial Port Figure 16-10. Programmable Serial Protocol (single transfers) SSPSCLK (when SCMODE = 0) SSPSCLK (when SCMODE = 1) SSPSCLK (when SCMODE = 2) SSPSCLK (when SCMODE = 3) Undefined SSPTXD T1 SSPRXD MSB LSB T2 T3 Undefined End of Transfer Data State T4 MSB LSB Undefined SSPSFRM (when SFRMP = 1) SSPSFRM T5 T6 (when SFRMP = 0) A9522-02 Table 16-2.
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Network SSP Serial Port set) if the assertion of frame is not before the MSB is sent (For example, T5 <= T2 if SSCR1[SFRMDIR] is set). Transmit Data transitions from the “End of Transfer Data State” to the next MSB value upon the assertion of frame. The start delay field should be programmed to 0 whenever SSPSCLK or SSPSFRM is configured as an input. 16.4.4 Hi-Z on SSPTXD The PXA255 processor NSSP supports placing SSPTXD into Hi-Z during idle times instead of driving SSPTXD.
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Network SSP Serial Port Figure 16-12. TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=1 SSPSCLK SSPSFRM SSPTXD SSPRXD Undefined Bit[N] Bit[N-1] Bit[1] Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0] MSB 4 to 32 Bits Undefined LSB A9975-01 Note: 16.4.4.2 If SSPSCLK is an input, the device driving SSPSCLK must provide another clock edge to cause the TXD line to go to Hi-Z. Motorola SPI When SSCR1[TTE] is 0, the SSP behaves as described in Section 16.4.3.2.
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Network SSP Serial Port Figure 16-14. National Semiconductor Microwire with SSCR1[TTE]=1 SSPSCLK SSPSFRM Bit[7] or Bit[15] SSPTXD Bit[0] 8 or 16-Bit Control Undefined SSPRXD Bit[N] Undefined Undefined Bit[0] 4 to 32 Bits A9977-01 Note: 16.4.4.4 SSCR1[TTELP] must be 0 for National Semiconductor Microwire. Programmable Serial Protocol When SSCR1[TTE] is 0, the SSP behaves as described in Section 16.4.3.4.
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Network SSP Serial Port Figure 16-16. PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (master to frame) SSPSCLK (when SCMODE = 0) SSPSCLK (when SCMODE = 1) SSPSCLK (when SCMODE = 2) SSPSCLK (when SCMODE = 3) SSPTXD MSB T1 T2 Undefined SSPRXD LSB T3 T4 LSB MSB Undefined SSPSFRM (when SFRMP = 1) T5 SSPSFRM T6 (when SFRMP = 0) A9979-01 SSCR1[TTELP] can only be set to 1 in PSP mode if the SSP is a slave to frame.
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Network SSP Serial Port 16.4.5 FIFO Operation Two separate and independent FIFOs are present for transmit (to peripheral) and receive (from peripheral) serial data. FIFOs are filled or emptied by programmed I/O or DMA bursts. 16.4.5.1 Using Programmed I/O Data Transfers The PXA255 processor can perform FIFO filling and emptying in response to an interrupt from the FIFO logic. Each FIFO has a programmable trigger threshold at which an interrupt is triggered.
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Network SSP Serial Port 16.5 Register Descriptions Each SSP consists of seven registers: three control, one data, one status, one time-out, and one test. • The SSP control registers (SSCR0, SSCR1) configure the baud rate, data length, frame format, data-transfer mechanism, and port enabling. They also permit setting the FIFO trigger threshold that triggers an interrupt. • Access all registers using aligned words. Note: Write the SSP registers after a reset but before the SSP is enabled.
PAGE 559
Network SSP Serial Port Table 16-3.
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Network SSP Serial Port Table 16-3. SSCR0 Bit Definitions (Sheet 2 of 2) ? ? Bits ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 Name 0 0 0 0 0 0 7 6 0 ? 5 4 3 2 0 0 0 0 1 0 0 0 DSS 8 FRF 11 10 9 SCR reserved ? 20 19 18 17 16 15 14 13 12 EDSS 31 30 29 28 27 26 25 24 23 22 21 Network SSP Serial Port reserved SSCR0 SSE 0x4140_0000 Description DATA SIZE SELECT: Used in conjunction with EDSS to select the size of the data transmitted and received by the SSP.
PAGE 561
Network SSP Serial Port Table 16-4.
PAGE 562
Network SSP Serial Port Table 16-4.
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Network SSP Serial Port Table 16-5.
PAGE 564
Network SSP Serial Port Table 16-5.
PAGE 565
Network SSP Serial Port Setting any of these bits also causes the corresponding status bit(s) to be set in the SSP Status Register (SSSR). The interrupt or service request caused by the setting of one of these bits remains active until the bit is cleared. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 16-7.
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Network SSP Serial Port Bits that cause an interrupt signal the request as long as the bit is set. The interrupt clears when the bits clear. Read and write bits are called status bits (status bits are referred to as sticky and once set by hardware, they must be cleared by software); Read-only bits are called flags. Writing a 1 to a status bit clears it; writing a 0 has no effect. Read-only flags are set and cleared by hardware; writes have no effect.
PAGE 567
Network SSP Serial Port Table 16-8.
PAGE 568
Network SSP Serial Port Table 16-8.
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Network SSP Serial Port As the system accesses the register, FIFO control logic transfers data automatically between the registers and FIFOs as fast as the system moves it. Unless attempting a write to a full transmit FIFO, data in the FIFO shifts up or down to accommodate the new word(s). Status bits show users whether the FIFO is full, above the programmable trigger threshold, below the programmable trigger threshold or empty.
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Network SSP Serial Port 16-30 Intel® PXA255 Processor Developer’s Manual
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Hardware UART 17 This chapter describes the signal definitions and operations of the PXA255 processor hardware UART (HWUART) port. The HWUART interface pins are available via either the PCMCIA general purpose I/O (GPIO) pins or the BTUART pins. Refer to Section 4.1.2, “GPIO Alternate Functions” for more information. When using the HWUART through the PCMCIA pins, they are driven at the same voltage level as the memory interface.
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Hardware UART — Non-Return-to-Zero (NRZ) encoding/decoding function — 64 byte transmit/receive FIFO buffers — Programmable receive FIFO trigger threshold — Auto baud-rate detection — Auto flow • Maximum baud rate of 921,600 bps.
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Hardware UART 17.3 Signal Descriptions Table 17-1 lists and describes each external signal that is connected to the UART module. The pins are connected to the PXA255 processor through GPIOs. Table 17-1. UART Signal Descriptions Name Type RXD Input TXD Description SERIAL INPUT – Serial data input to the receive shift register. In infrared mode, it is connected to the infrared receiver input. SERIAL OUTPUT – Serial data output to the communications link-peripheral, modem, or data set.
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Hardware UART Receive data sample counter frequency is 16 times the value of the bit frequency. The 16X clock is created by the baud rate generator. Each bit is sampled three times in the middle. Shaded bits in Figure 17-1 are optional and can be programmed by software. Each data frame is between seven and 12 bits long, depending on the size of the data programmed, whether parity is enabled, and the number of stop bits.
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Hardware UART 17.4.2.1 FIFO Interrupt Mode Operation 17.4.2.1.1 Receive Interrupt For a receive interrupt to occur, the receive FIFO and receive interrupts must be enabled. The Interrupt Identification register (IIR) bits 1 and 2 (IIR[IID]) change to show that receive data is available when the FIFO reaches its trigger threshold. IIR[IID] changes to show the next waiting interrupt when the FIFO drops below the trigger threshold. A change in IIR[IID] triggers an interrupt to the core.
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Hardware UART 17.4.2.3 FIFO DMA Mode Operation The UART has two DMA requests: one for transmit data service, and one for receive data service. DMA requests are generated in FIFO mode only. The requests are activated by setting IER[DMAE]. • Data Transmit Data Service – When IER[DMAE] is set, if the transmit FIFO is less than half full, the transmit-DMA request is generated. The DMA controller then writes data to the FIFO.
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Hardware UART Note: 17.4.2.6 Ensure that the DMA controller has completed the previous receive DMA requests before the error interrupt handler begins to clear the errors from the FIFO. If not, FIFO underflow could occur. Removing Trailing Bytes In DMA Mode When the number of entries in the receive FIFO is less than its trigger threshold, and no additional data is received, the remaining bytes are called trailing bytes.
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Hardware UART If the UART is to program the Divisor Latch registers, you can choose one of two methods for auto-baud calculation: table-based and formula-based. Set Auto-Baud Control register (ABR), bit 3 (ABR[ABT]) to select which method you want to use (refer to Section 17.5.8). When the formula method is used, any baud rate defined by the parameters in Section 17.5.3 can be programmed by the UART. The formula method works well for higher baud rates, but could possibly fail below 28.
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Hardware UART Figure 17-3. IR Transmit and Receive Example UART TRANSMIT SHIFT VALUE START BIT 1 0 0 0 1 1 0 0 STOP BIT IR ENCODER OUTPUT (TXD PIN VALUE) RXD PIN VALUE IR DECODER OUTPUT START BIT UART RECEIVE 1 0 0 0 1 0 1 0 SHIFT VALUE STOP BIT The top line in Figure 17-3 shows an asynchronous transmission as it is sent from the UART. The second line shows the pulses generated by the IR encoder at the TXD pin.
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Hardware UART 17.5 Register Descriptions 17.5.1 Receive Buffer Register (RBR) In non-FIFO mode, the RBR, shown in Table 17-2, holds the character(s) received by the UART’s Receive Shift Register. If the RBR is configured to use fewer than eight bits, the bits are rightjustified and the most significant bits (MSB) are zeroed. Reading the register empties the register and clears LSR[DR] (refer to Section 17.5.11, “Line Status Register (LSR)” on page 17-19).
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Hardware UART Load these divisor latches during initialization to ensure that the baud rate generator operates properly. If each divisor latch is loaded with a 0, the 16X clock stops. The divisor latches are accessed with a word write. The baud rate of the data shifted in to or out of a UART is given by the formula: 14.7456 MHz BaudRate = ---------------------------------( 16xDivisor ) For example, if the divisor is 24, the baud rate is 38400 bps. The divisor’s reset value is 0x0002.
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Hardware UART Enabling DMA requests also enables a separate error interrupt. For additional information see Section 17.4.2.5. Set bit 7 of the IER to enable DMA requests. The IER also contains the unit enable and NRZ coding enable control bits. Bits 7 through 4 are used differently from the standard 16550A register definition. Note: MCR[OUT2] is a global interrupt enable, and must be set to enable UART interrupts.
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Hardware UART 17.5.5 Interrupt Identification Register (IIR) The UART prioritizes interrupts in four levels (see Table 17-7) and records them in the IIR. The IIR stores information that indicates that a prioritized interrupt is pending and identifies the source of the interrupt. The Interrupt Identification Register (IIR) bit definitions are shown in Table 17-8. If additional data is received before a receiver time out interrupt is serviced, the interrupt is deasserted.
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Hardware UART Table 17-8. IIR Bit Definitions (Sheet 2 of 2) ? 0 reserved Reset ? ? ? ? ? ? ? Bits Name 4 ABL 3 TOD ? ? ? ? ? ? 6 ? ? ? ? ? ? ? ? ? ? 0 5 4 3 ? 0 0 2 1 0 0 nIP 7 IID 8 TOD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 ABL PXA255 Processor Hardware UART FIFOES Bit Interrupt Identification Register (IIR) reserved Physical Address 0x4160_0008 0 1 Description Autobaud Lock (Section 17.4.
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Hardware UART Table 17-9. Interrupt Identification Register Decode (Sheet 2 of 2) Interrupt ID bits Interrupt SET/RESET Function 3 2 1 0 Priority Fourth Highest IID[00] 0 0 0 0 Type Source RESET Control Clear to send, data set ready, ring indicator, received line signal detect. Modem Status Reading the Modem Status register. Non Prioritized Interrupts: ABL 4 Autobaud Lock Autobaud circuitry has locked onto indication. the baud rate. None 17.5.
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Hardware UART Table 17-10.
PAGE 587
Hardware UART 17.5.8 Auto-Baud Control Register (ABR) The ABR, shown in Table 17-12, controls the functionality and options for auto-baud-rate detection within the UART. Through this register, users can enable or disable the auto-baud lock interrupt, direct either the processor or UART to program the final baud rate in the Divisor Latch registers, and choose between the two methods used to calculate the final baud rate.
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Hardware UART This is a read-only register. Ignore reads from reserved bits. Table 17-13. ACR Bit Definitions Physical Address 0x4160_002C Bit Autobaud Count Register (ACR) PXA255 Processor Hardware UART 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 reserved Reset ? ? ? ? ? ? ? Bits Name 31:16 — 15:0 ACR 17.5.10 ? ? 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 Count Value ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 Description reserved Number of 14.
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Hardware UART Table 17-14. LCR Bit Definitions (Sheet 2 of 2) Reset ? ? ? Bits ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Name ? ? ? ? ? ? 5 4 3 2 0 0 0 0 0 0 1 0 WLS 6 STB reserved 7 PEN 8 EPS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 STKYP PXA255 Processor Hardware UART SB Bit Line Control Register (LCR) DLAB Physical Address 0x4160_000C 0 0 Description EVEN PARITY SELECT 4 EPS Even parity select bit. If PEN = 0, EPS is ignored.
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Hardware UART Table 17-15. LSR Bit Definitions (Sheet 1 of 2) ? ? ? ? ? ? Bits Name 31:8 — ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4 3 2 1 0 DR ? 5 OE Reset 6 FE reserved 7 PE 8 BI 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 TDRQ PXA255 Processor Hardware UART TEMT Bit Line Status Register (LSR) FIFOE Physical Address 0x4160_0014 0 1 1 0 0 0 0 0 Description reserved FIFO ERROR STATUS 7 FIFOE In non-FIFO mode, this bit is 0.
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Hardware UART Table 17-15.
PAGE 592
Hardware UART Table 17-16.
PAGE 593
Hardware UART Table 17-16. MCR Bit Definitions (Sheet 2 of 2) 6 ? ? ? reserved Reset ? ? ? ? ? Bits ? ? ? ? ? ? ? ? ? ? ? ? ? Name ? ? ? ? ? 5 4 3 2 1 0 reserved 7 RTS 8 OUT2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 reserved PXA255 Processor Hardware UART AFE Bit Modem Control Register (MCR) LOOP Physical Address 0x4160_0010 0 0 0 ? 0 ? Description REQUEST TO SEND Controls the status of the nRTS pin when the AFE bit is clear.
PAGE 594
Hardware UART Table 17-17. MSR Bit Definitions (Sheet 2 of 2) PXA255 Processor Hardware UART 8 7 6 5 ? ? ? ? reserved Reset ? ? ? ? ? Bits ? ? ? ? ? ? ? ? ? ? 4 3 ? ? ? Name ? ? ? ? ? 1 2 1 ? ? 0 DCTS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 CTS Bit Modem Status Register (MSR) reserved Physical Address 0x4160_0018 ? 0 Description CLEAR TO SEND 4 Complement of the clear to send (nCTS) input.
PAGE 595
Hardware UART Table 17-19.
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Hardware UART Table 17-20.
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Hardware UART Intel® PXA255 Processor Developer’s Manual 17-27
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