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Intel® PXA26x Processor Family

Developer’s Manual

March, 2003

Order Number: 278638-002

Summary of content (624 pages)

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Intel® PXA26x Processor Family Developer’s Manual March, 2003 Order Number: 278638-002
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Contents INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Contents Contents 1 Introduction...................................................................................................................................1-1 1.1 1.2 2 Intel® XScale™ Core Features .........................................................................................1-1 System Integration Features..............................................................................................1-2 1.2.1 Memory Controller ............................................................
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Contents 3 Clocks and Power Manager .........................................................................................................3-1 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 4 System Integration Unit ................................................................................................................ 4-1 4.1 iv Clock Manager Introduction...............................................................................................3-1 Power Manager Introduction.......................
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Contents 4.2 4.3 4.4 4.5 5 Direct Memory Access Controller .................................................................................................5-1 5.1 5.2 5.3 5.4 5.5 6 4.1.2 GPIO Alternate Functions.....................................................................................4-3 4.1.3 GPIO Register Definitions.....................................................................................4-7 4.1.4 GPIO Register Locations ...................................................
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Contents 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 7 Liquid Crystal Display Controller ..................................................................................................7-1 7.1 7.2 vi Functional Description .......................................................................................................6-2 6.2.1 SDRAM Interface Overview.................................................................................. 6-2 6.2.
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Contents 7.3 7.4 7.5 7.6 8 Synchronous Serial Port Controller ..............................................................................................8-1 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 7.2.3 Resetting the Controller ........................................................................................7-5 Detailed Module Descriptions ............................................................................................7-5 7.3.1 Input FIFOs ...............................................
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Contents 9.4 9.5 9.6 9.7 9.8 9.9 10 Universal Asynchronous Receiver/Transmitter ..........................................................................10-1 10.1 10.2 10.3 10.4 10.5 11 Feature List......................................................................................................................10-1 Overview..........................................................................................................................10-2 10.2.1 Full Function UART ....................
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Contents 11.3 11.4 12 11.2.1 Four-Position Pulse Modulation ..........................................................................11-2 11.2.2 Frame Format .....................................................................................................11-3 11.2.3 Address Field......................................................................................................11-4 11.2.4 Control Field ................................................................................................
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Contents 12.6.3 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 1, 6, or 11....12-26 12.6.4 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 2, 7, or 12....12-28 12.6.5 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 3, 8, or 13....12-31 12.6.6 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 4, 9, or 14....12-33 12.6.7 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 5, 10, or 15..12-35 12.6.8 UDC Interrupt Control Register 0 (UICR0) ...............
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Contents 14.4 14.5 14.6 14.7 15 14.3.5 Receive FIFO Errors ...........................................................................................14-5 14.3.6 Trailing Bytes ......................................................................................................14-5 Serial Audio Clocks and Sampling Frequencies..............................................................14-5 Data Formats ....................................................................................................
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Contents 15.5.5 MMC_CMDAT Register ....................................................................................15-25 15.5.6 MMC_RESTO Register ....................................................................................15-26 15.5.7 MMC_RDTO Register.......................................................................................15-27 15.5.8 MMC_BLKLEN Register ...................................................................................15-28 15.5.9 MMC_NOB Register .............
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Contents 17.6 18 17.5.4 Interrupt Enable Register (IER) ........................................................................17-13 17.5.5 Interrupt Identification Register (IIR) .................................................................17-14 17.5.6 FIFO Control Register (FCR) ............................................................................17-17 17.5.7 Receive FIFO Occupancy Register (FOR) .......................................................17-18 17.5.
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Contents 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 6-30 6-31 6-32 6-33 7-1 7-2 7-3 7-4 7-5 7-6 7-8 7-9 7-10 7-7 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 8-1 8-2 8-3 8-4 9-1 9-2 9-3 9-4 xiv 32-Bit Burst-of-Eight ROM or Flash Read Timing Diagram (MSC0:RDF = 4, MSC0:RDN = 1, MSC0:RRR = 1)............................................................................................
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Contents 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 10-1 10-2 10-3 10-4 11-1 11-2 11-3 12-1 12-2 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 14-1 14-2 14-3 15-1 15-2 15-3 15-4 15-5 15-6 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 Acknowledge on the I2C Bus.....................................................................................................9-8 Clock Synchronization During the Arbitration Procedure.........................................................
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Contents 16-10 16-11 16-12 16-13 16-14 16-15 16-16 16-17 17-1 17-2 17-3 17-4 18-1 18-2 Programmable Serial Protocol (single transfers)...................................................................16-12 TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=0.................................................................16-13 TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=1.................................................................16-14 Motorola SPI with SSCR[TTE]=1..................................................
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Contents 3-26 3-27 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 4-41 4-42 4-43 4-44 4-45 4-46 4-47 4-48 CCLKCFG Bit Definitions.........................................................................................................3-40 PWRMODE Bit Definitions.......................................................................................................
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Contents 4-49 4-50 4-51 4-52 4-53 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 6-30 6-31 6-32 xviii OS Timer Register Locations ..................................................................................................4-42 PWM_CTRLn Bit Definitions ...................................................................................................
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Contents 6-33 6-34 6-35 6-36 6-37 6-38 6-39 6-40 6-41 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 8-1 8-2 8-3 8-4 8-5 8-6 8-7 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 10-1 10-2 10-3 10-4 10-5 Common Memory Space Read Commands ............................................................................6-63 Attribute Memory Space Write Commands .............................................................................6-63 Attribute Memory Space Read Commands ....
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Contents 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 12-16 12-17 12-18 12-19 12-20 12-21 12-22 12-23 12-24 12-25 12-26 xx Divisor Latch High Register – DLH..........................................................................................10-8 Interrupt Enable Register – IER...........................................................
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Contents 12-27 12-28 12-29 12-30 12-31 12-32 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 13-17 13-18 13-19 13-20 13-21 13-22 13-23 13-24 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 UDC Endpoint x Data Register, Where x is 1, 6, or 11..........................................................12-47 UDC Endpoint x Data Register, Where x is 2, 7, or 12..........................................................
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Contents 15-9 15-10 15-11 15-12 15-13 15-14 15-15 15-16 15-17 15-18 15-19 15-20 15-21 15-22 15-23 15-24 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 17-12 17-13 17-14 17-15 17-16 17-17 17-18 17-19 17-20 18-1 18-2 xxii MMC_SPI Register................................................................................................................15-24 MMC_CMDAT Register .....................................................................
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Contents Revision History Date Revision October 2002 Public Release -001 March 2003 Release -002 Intel® PXA26x Processor Family Developer’s Manual Description Released to the public Added fast wake-up and 33-MHz idle mode.
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Contents xxiv Intel® PXA26x Processor Family Developer’s Manual
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Introduction 1 The Intel® PXA26x Processor Family is a 32-bit, multi-chip device which combines a processor based on Intel® XScale™ microarchitecture and Intel StrataFlash® memory. (Intel StrataFlash® memory is available on some versions.) The PXA26x processor family provides industry-leading MIPS/mW performance for handheld computing and cell phone applications. The PXA26x processor family is available in a 13x13mm 294-pin TF-BGA package.
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Introduction 1.2 System Integration Features The PXA26x processor family features are: • • • • • • • • • • • • • • • • • • • • • • • 1.2.1 Integrated synchronous Intel StrataFlash® memory on some versions Single-ended universal serial bus client interface Network synchronous serial protocol port Audio synchronous serial protocol port Low voltage support (2.775 volts) for VCCQ Low voltage support (2.
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Introduction The 3.6864-MHz crystal drives a core phase locked loop (PLL) and a peripheral PLL. The PLLs produce selected clock frequencies to run particular functional blocks. The 32.768-KHz crystal provides an optional clock source that must be selected after a hard reset. This clock drives the real time clock, power management controller, and interrupt controller. The 32.768-KHz crystal is on a separate power island to provide an active clock while the processor is in sleep mode.
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Introduction 1.2.8 Multimedia Card (MMC) Controller The MMC controller provides a serial interface to standard memory cards. The controller supports up to two cards in either MMC or SPI modes with serial data transfers up to 20 Mbps. The MMC controller has FIFOs that support DMA access to and from memory. 1.2.9 Fast Infrared (FIR) Communication Port The FIR communication port is based on the 4-Mbps Infrared Data Association (IrDA) Specification.
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Introduction The STUART’s transmit and receive pins are multiplexed with the fast infrared communication port. 1.2.14 Real-Time Clock (RTC) The RTC can be clocked from either the 3.6864-MHz crystal or from an optional 32-KHz crystal. A system with a 32.768-KHz crystal consumes less power during sleep versus a system using only the 3.6864-MHz crystal. The RTC provides a constant frequency output with a programmable alarm register. This alarm register can be used to wake up the processor from sleep mode.
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Introduction 1.2.20 Network Synchronous Serial Protocol Port The PXA26x processor family has an SSP port optimized for connection to other network ASICs. This NSSP adds a Hi-Z function to TXD, the ability to control when Hi-Z occurs, and swapping the TXD/RXD pins. This port is not multiplexed with other interfaces. 1.2.21 Audio Synchronous Serial Protocol Port The PXA26x processor family has an SSP port optimized for connection to audio ASICs.
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System Architecture 2.1 2 Overview The Intel® PXA26x Processor Family is an integrated system-on-a-chip microprocessor for high performance, low-power-portable handheld and handset devices. It incorporates the Intel® XScale™ microarchitecture with on-the-fly frequency scaling and sophisticated power management to provide industry leading MIPs/mW performance. The processor is ARM* Version 5TE instruction set compliant (excluding floating point instructions) and follows the ARM* programmer’s model.
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System Architecture Figure 2-1. Block Diagram RTC Color or Grayscale LCD Controller OS Timer PWM(2) Int. Controller Clocks & Power Man.
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System Architecture 2.3 Intel® XScale™ Microarchitecture Implementation Options The processor incorporates the Intel® XScale™ microarchitecture. This core contains implementation options which an Application Specific Standard Product (ASSP) may elect to implement or omit. This section describes these options. Most of these options are specified within the coprocessor register space.
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System Architecture 2.3.3 Coprocessor 14 Register 6 and 7– Clock and Power Management These registers allow software to use the clocking and power management modes. The valid operations are described in Table 3-25, “Coprocessor 14 Clock and Power Management Summary” on page 3-40. 2.3.4 Coprocessor 15 Register 0 – ID Register Definition The Coprocessor 15 register may be read by software to determine the device type and revision.
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System Architecture Table 2-2. ID Register Bitmap and Bit Definitions (Read-only) (Sheet 2 of 2) 1 0 0 0 1 0 1 0 0 Core 0 Revision 0 1 0 1 1 0 1 6 0 0 5 4 3 0 0 0 2 1 Product 0 7 Revision 0 Core 1 generation 0 8 Product 1 Version 1 Architecture 0 Trademark Reset CP15 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Implementation Bit ID Number CP15 Register 0 1 0 0 1 This field is specific to each ASSP.
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System Architecture Loads and stores to internal addresses are generally completed more quickly than those issued to external addresses. The difference in completion time allows one operation to be received before another operation, but completed after the second operation. In the following sequence, the store to the address in r4 is completed before the store to the address in r2 because the first store waits for memory in the queue while the second is not delayed.
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System Architecture Note: Clearing interrupts may take a delay. To allow the status bit to clear before returning from an interrupt service routine (ISR), clear the interrupt early in the routine. 2.7 Reset Table 2-4 shows each pin’s state after each type of reset. Table 2-4.
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System Architecture Byte and halfword accesses to internal registers are not permitted and yield unpredictable results. Register space, where a register is not specifically mapped, is defined as reserved space. Reading or writing reserved space causes unpredictable results. The processor does not use all register bit locations. The unused bit locations are marked reserved and are allocated for future use. Write reserved bit locations as zeros.
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System Architecture • Sleep mode – low power mode that does not save state but keeps I/Os powered. While the RTC, power manager, and clock module states are saved, coprocessor 14 is not. Note: In low power modes, ensure that input pins are not floating and output pins are not driven by an external device in conflict with how the processor is driving that pin. In either case, the system draws excess current.
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System Architecture Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 2 of 12) Pin Name Type Signal Descriptions Reset State Sleep State nSDCS[0] OCZ Driven High Driven High nSDCS[1] OC Driven High Driven High nSDCS[2]/ GPIO[86] ICOC nSDCS[3]/ GPIO[87] ICOC DQM[3:0] OCZ nSDRAS OCZ nSDCAS OCZ SDCKE[0] OC SDRAM CS FOR BANKS 0 THROUGH 3 (output): Connect to the chip select (CS) pins for SDRAM.
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System Architecture Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 3 of 12) Pin Name nCS[5]/ GPIO[33] nCS[4]/ GPIO[80] nCS[3]/ GPIO[79] nCS[2]/ GPIO[78] nCS[1]/ GPIO[15] Type Signal Descriptions Reset State Sleep State ICOCZ ICOCZ STATIC CHIP SELECTS (output): ICOCZ Chip selects to static memory devices such as ROM and Pulled High flash. Individually programmable in the memory Note [1] configuration registers. nCS[5:0] can be used with variable latency I/O devices.
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System Architecture Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 4 of 12) Pin Name nPIOR/ GPIO[50] Type ICOCZ Signal Descriptions PCMCIA I/O READ (output): Reset State Sleep State Pulled High Note [1] Note [5] Pulled High Note [1] Note [5] Pulled High Note [1] Note [5] Pulled High Note [1] Note [5] Pulled High Driven low by the PCMCIA card to extend the length of the Note [1] transfers to/from the PXA26x processor family.
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System Architecture Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 5 of 12) Pin Name Type Signal Descriptions Reset State Sleep State LCD DISPLAY DATA (output): L_DD[12]/ GPIO[70] ICOCZ Transfers pixel information from the LCD Controller to the Pulled High external LCD panel. Note [1] Note [3] RTC clock. (output) Real time clock 1 Hz tick.
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System Architecture Table 2-6.
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System Architecture Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 7 of 12) Pin Name FFTXD/ GPIO[39] Type Signal Descriptions Reset State Sleep State FULL FUNCTION UART TRANSMIT (output) ICOCZ MMC CHIP SELECT 1 (output): Pulled High Note [1] Note [3] Pulled High Note [1] Note [3] Pulled High Note [1] Note [3] Pulled High Note [1] Note [3] Chip select 1 for the MMC Controller.
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System Architecture Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 8 of 12) Pin Name Type Signal Descriptions Reset State Sleep State AC97 Controller and I2S Controller Pins AC97 AUDIO PORT BIT CLOCK (input): AC97 clock is generated by Codec 0 and fed into the PXA26x processor family and Codec 1. AC97 AUDIO PORT BIT CLOCK (output): BITCLK/ GPIO[28] ICOCZ AC97 clock is generated by the PXA26x processor family.
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System Architecture Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 9 of 12) Pin Name Type GPIO[14:2] ICOCZ GPIO[22:21] ICOCZ GPIO[85] ICOCZ Signal Descriptions GENERAL PURPOSE I/O: More wake-up sources for sleep mode. GENERAL PURPOSE I/O: Additional General Purpose I/O pins. GENERAL PURPOSE I/O: Additional General Purpose I/O pins.
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System Architecture Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 10 of 12) Pin Name Type Signal Descriptions Reset State Sleep State Miscellaneous Pins BOOT SELECT PINS (input): BOOT_SEL [2:0] IC Indicates type of boot device. See Section 18.1, “Initialization” for information on configuring BOOT_SEL for proper flash initialization. Input Input Driven High Driven low while entering sleep mode. Driven high when sleep exit sequence begins.
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System Architecture Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 11 of 12) Pin Name Type Signal Descriptions Reset State Sleep State JTAG TEST MODE SELECT (input): TMS IC TCK IC TEST IC TESTCLK IC Selects the test mode required from the JTAG controller. This pin has an internal pull-up resistor. JTAG TEST CLOCK (input): Clock for all transfers on the JTAG test interface. TEST MODE (input): Reserved. Must be grounded. TEST CLOCK (input): Reserved.
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System Architecture Table 2-6.
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System Architecture Table 2-7. Pin Description Notes Note Description [1] GPIO Reset Operation: Configured as GPIO inputs by default after any reset. The input buffers for these pins are disabled to prevent current drain and the pins are pulled high with 10K to 60K internal resistors. The input paths must be enabled and the pull-ups turned off by clearing the Read Disable Hold (RDH) bit described in Section 3.5.7, “Power Manager Sleep Status Register” on page 3-27.
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System Architecture Table 2-8.
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System Architecture Table 2-8.
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System Architecture Table 2-8.
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System Architecture Table 2-8.
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System Architecture Table 2-8. Register Address Summary (Sheet 6 of 13) Unit Address Register Symbol Register Description 0x4040 0064 through — reserved SADR Serial Audio Data Register (TX and RX FIFO access Register).
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System Architecture Table 2-8.
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System Architecture Table 2-8.
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System Architecture Table 2-8.
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System Architecture Table 2-8.
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System Architecture Table 2-8.
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System Architecture Table 2-8.
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System Architecture Table 2-8. Register Address Summary (Sheet 13 of 13) Unit 2.
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System Architecture Figure 2-2.
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System Architecture Figure 2-3.
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System Architecture 2-36 Intel® PXA26x Processor Family Developer’s Manual
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Clocks and Power Manager 3 The clocks and power manager for the Intel® PXA26x Processor Family controls the clock frequency to each module and manages transitions between the different power manager operating modes to optimize both computing performance and power consumption. The PXA26x processor family clocks and power manager supports 400-MHz run mode, and CKEN bits for the NSSP, ASSP, and HWUART. Also, it includes nine new GPIOs that must be defined in the Power Manager Sleep State registers. 3.
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Clocks and Power Manager 3.2 Power Manager Introduction The clocks and power manager can place the processor in one of three resets. • Hardware reset (nRESET asserted) is a nonmaskable total reset. Use hardware reset at power up or when no system information requires preservation. • Watchdog reset is asserted through the watchdog timer and resets the system with the exception of the clocks and power manager. Use his reset as a code monitor.
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Clocks and Power Manager Figure 3-1 shows a functional representation of the clocking network. “L” is in the core PLL. The PXbus is the internal bus between the core, the DMA/bridge, the LCD controller, and the memory controller as shown in Figure 3-1. This bus is clocked at 1/2 the run mode frequency. For optimal performance, the PXbus should be clocked as fast as possible. For example, if a target core frequency of 200 MHz is desired use 200-MHz run mode instead of 200-MHz turbo mode with run at 100 MHz.
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Clocks and Power Manager 3.3.1 32.768-KHz Oscillator The 32.768-KHz oscillator is a low-power, low-frequency oscillator that clocks the RTC and power manager. The 32.768-KHz oscillator is disabled out of hardware reset so the RTC and power manager blocks use the 3.6864-MHz oscillator instead. Software writes the Oscillator On bit in the Oscillator Configuration Register to enable the 32.768-KHz oscillator. This configures the RTC and power manager to use the 32.768-KHz oscillator after it stabilizes. 32.
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Clocks and Power Manager Table 3-1. Core PLL Output Frequencies for 3.6864-MHz Crystal 3.3.4 L M Turbo Mode Frequency (MHz) for Values “N” and Core Clock Configuration Register (CCCR[15:0]) PXbus programming for Values of “N”: Frequency (MHz) 1.00 1.50 2.00 3.00 (Run) 27 1 99.5 @.85 V — 199.1 @1.0 V 298.6 @1.1 V 32 1 118.0 @1.0 V — 235.9 @1.1 V 36 1 132.7 @1.0 V — 40 1 147.5 @1.0 V 45 1 27 MEM, LCD Frequency (MHz) SDRAM max Freq (MHz) 50 99.5 99.5 353.9 @1.3 V 59 118.0 59.
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Clocks and Power Manager 3.3.5 147.46-MHz Peripheral Phase Locked Loop The 147.46-MHz PLL is the clock source for many of the peripheral blocks’ external interfaces. These interfaces require: ~14.75 MHz for the UARTs, 12.288 MHz for the AC97, and variable frequencies for I2S. The generated frequency may not exactly match the required frequency due to the choice of crystal and the lack of a perfect least common multiple between the units.
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Clocks and Power Manager 3.4.1 Hardware Reset To invoke a hardware reset and reset all units in the processor to a known state, assert the nRESET pin. Hardware reset is only intended to be used for power up and complete resets. 3.4.1.1 Invoking Hardware Reset Hardware reset is invoked when the nRESET pin is pulled low by an external source. The processor does not provide a method of masking or disabling the propagation of the external pin value.
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Clocks and Power Manager 3.4.2.2 Behavior During Watchdog Reset During watchdog reset, all units except the real time clock and parts of the clocks and power manager maintain their defined reset conditions. All pins except the oscillator pins assume their reset conditions and the nBATT_FAULT and nVDD_FAULT pins are ignored. All dynamic RAM contents are lost during watchdog reset because the memory controller receives a full reset.
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Clocks and Power Manager GPIO reset does not function in sleep mode because all GPIO pins’ alternate function inputs are disabled. External wake-up sources must be routed through one of the enabled GPIO wake-up sources (see Section 3.5.3, on page 3-25 for details) during sleep mode. GP[1] may be enabled as a wake-up source. 3.4.3.2 Behavior During GPIO Reset During GPIO reset, most, but not all, internal registers and processes are held at their defined reset conditions.
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Clocks and Power Manager 3.4.5.1 Entering Turbo Mode The ratio between the run mode processor clock frequency and the turbo mode processor clock frequency is programmed in CCCR[N]. The value in CCCR[N], and any other appropriate clock configurations, must be programmed through the frequency change sequence. To simultaneously change turbo mode and enter the frequency change sequence, use the steps to change the frequency change sequence.
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Clocks and Power Manager During idle mode these resources are active: • System unit modules (real-time clock, operating system timer, interrupt controller, generalpurpose I/O, and the clocks and power manager) • Peripheral unit modules (DMA controller, LCD controller, and all other peripheral units) • Memory controller resources 3.4.6.1 Entering Idle Mode During idle mode, the clocks to the CPU core stop.
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Clocks and Power Manager Software must then shut down the system and enter sleep mode. See Section 3.4.9.3, “Entering Sleep Mode” for more details. 3.4.7 33-MHz Idle Mode 33-MHz idle mode has the lowest power consumption of any idle mode. The run mode frequency selected in the Core Clock Configuration Register (CCCR) directly affects the processor idle mode power consumption. Faster run mode frequencies consume more power.
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Clocks and Power Manager 3. Perform a frequency change sequence to 33MHz mode. The CCCR value for this mode is 0x13F 4. Enter idle mode by selecting the PWRMODE[M] bit (refer to Section 3.7.2) 3.4.7.2 Behavior in 33-MHz Idle Mode In 33-MHz idle mode the CPU clocks are stopped. While in 33-MHz idle mode these features of the processor all operate normally: the RTC timer, the OS timers including the watchdog timer, and the GPIO interrupt capabilities.
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Clocks and Power Manager 2. Disable the LCD controller or configure it to avoid the effects of an interruption in the LCD clocks and data from the processor. 3. Configure peripheral units to handle a lack of DMA service for up to 500 µs. If a peripheral unit can not function for 500 µs without DMA service, disable it. 4. Disable peripheral units that can not accommodate a 500 µs interrupt latency. The interrupts generated during the frequency change sequence are serviced when the sequence exits. 5.
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Clocks and Power Manager If hardware or watchdog reset is asserted during the frequency change sequence, the DRAM contents are lost because all states, including memory controller configuration and information about the previous frequency change sequence, are reset. If GPIO reset is asserted during the frequency change sequence, the SDRAM contents are lost during the GPIO reset exit sequence if the SDRAM is not in self-refresh mode and the exit sequence exceeds the refresh interval.
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Clocks and Power Manager • A power enable input pin that enables the primary supply output connected to VCC and PLL_VCC. This pin must be connected to the processor’s PWR_EN pin. To support fast sleep wake up by maintaining power during sleep, the regulator should be software configurable to ignore PWR_EN. When PWR_EN is not used, VCC and PLL_VCC may be powered on before or simultaneously with VCCN and VCCQ.
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Clocks and Power Manager — PM GPIO Sleep State registers (PGSR0, PGSR,1 and PGSR2) — PM Wake-up Enable register (PWER) — PM GPIO Falling-edge Detect Enable and PM GPIO Rising-edge Detect Enable registers (PFER and PRER) — OPDE bit in the Power Manager Configuration Register (PCFR) — IDAE bit in PMCR Note: 3.4.9.3 Clear the PCFR[OPDE] bit to enable the 3.6864-MHz oscillator during sleep when fast-sleep wake up is selected using the PMFWR[FWAKE] bit.
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Clocks and Power Manager in software by reading the Saved Program Status Register (SPSR) to see if the previous context was executing in abort mode. To enter sleep mode, software must complete this sequence: 1. Software uses external memory and the Power Manager Scratch Pad Register (PSPR) to preserve critical states. 2. Software sets sleep mode in PWRMODE[M]. An interrupt immediately aborts sleep mode and normal processing resumes. 3. The CPU waits until all instructions in the pipeline are complete. 4.
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Clocks and Power Manager Refer to Table 2-6, “Pin & Signal Descriptions for the PXA26x Processor Family” on page 2-9 for the PXA26x processor family pin states during sleep mode reset and other resets. 3.4.9.5 Exiting Sleep Mode Sleep mode exits when hardware reset is asserted. Hardware reset entry and exit sequences take precedence over sleep mode.
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Clocks and Power Manager — The power manager wake-up source registers (PWER, PRER, and PFER) are loaded with 0x0000 0003, their wake-up default state. This limits the potential wake-up sources to a rising or falling edge on GPIO[0] or GPIO[1]. The wake-up fault state prevents spurious events from causing an unwanted wake-up while the battery is low or the power supply is at risk. The fault state is also the default state after a hardware reset. 2. The PLL clock generators are disabled. 3.
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Clocks and Power Manager . Fault1 Sleep PWR_EN is asserted x x 4 External power ramp (if core supply was disabled in sleep) x x 5 Enable 3.6864 MHz oscillator if OPDE and OOK are set x x 6 Wait for 3.
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Clocks and Power Manager Table 3-6. Power and Clock Supply Sources and States During Power Modes Power Mode Supply Source Module Turbo Pw Ck Idle Freq Change T R Off changing (R/T) Memory Controller LCD Controller Mem On VCC DMA Controller On Off Off On On On 3.686MHz Osc Interrupts VCC/ 32.768Reg KHz Osc (V/R) GP[3:0], PM HV/ Dynamic/ Batt pads, Osc Static (H/B) pads (D/S) General IO On PLL OS timer Power Manager On On General Periphs.
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Clocks and Power Manager 3.5.1 Power Manager Control Register (PMCR) Use the PMCR, refer to Table 3-7, to select how sleep mode is entered when the nVDD_FAULT or the nBATT_FAULT pin is asserted low. When the IDAE bit is set, an imprecise data abort indication is sent to the CPU. The CPU then performs an abort routine. Software must ensure that the abort routine sets the sleep mode configuration in the PWRMODE register (see Section 3.7.2, “Power Mode Register (PWRMODE)”).
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Clocks and Power Manager 3.5.2 Power Manager General Configuration Register (PCFR) Use the PCFR, refer to Table 3-8, to configure power manager functions in the processor. When the OPDE bit is set, it allows the 3.6864-MHz oscillator to be disabled during sleep mode. The OPDE bit is cleared in hardware, watchdog, and GPIO resets. The Float PCMCIA (FP) and Float Static Memory (FS) bits control the state of the PCMCIA control pins and the static memory control pins during sleep mode.
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Clocks and Power Manager 3.5.3 Power Manager Wake-Up Enable Register (PWER) PWER, refer to Table 3-9, shows the location of all wake up source enable bits. If a GPIO is used as a sleep-mode wake up source, program it as an input in the GPDR and set either one or both of the corresponding bits in the PRER and PFER. When the IDAE bit is zero and a fault condition is detected on the nVDD_FAULT or nBATT_FAULT pin, PWER is set to 0x0000 0003 and only allows GP[1:0] as wake-up sources.
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Clocks and Power Manager 3.5.4 Power Manager Rising-Edge Detect Enable Register (PRER) The PRER, refer to Table 3-10, determines whether the GPIO pin enabled via the PWER register causes a sleep-mode wake up on the GPIO pin’s rising edge. When the IDAE bit is zero and a fault condition is detected on the nVDD_FAULT or nBATT_FAULT pin, PRER is set to 0x0000 0003. This enables rising edges on GP[1:0] to act as wake up sources.
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Clocks and Power Manager 3.5.5 Power Manager Falling-Edge Detect Enable Register (PFER) The PFER, refer to Table 3-11, determines if the GPIO pin enabled via the PWER register causes a sleep-mode wake up on the GPIO pin’s falling edge. When the IDAE bit is zero and a fault condition is detected on the nVDD_FAULT or nBATT_FAULT pin, PFER is set to 0x0000 0003. This enables falling edges on GP[1:0] to act as wake up sources.
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Clocks and Power Manager 3.5.6 Power Manager GPIO Edge Detect Status Register (PEDR) The PEDR, refer to Table 3-12, indicates which of the GPIO pins enabled via the PWER, PRER, and PFER registers caused a sleep-mode wake up. The bits in PEDR can only be set on a rising or falling edge on a given GPIO pin. If PRER is set, the bits in PEDR can only be set on a rising edge. If PFER is set, the bits in PEDR can only be set on a falling edge. To reset a bit in PEDR to zero, write a 1 to it.
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Clocks and Power Manager 3.5.7 Power Manager Sleep Status Register (PSSR) The PSSR, refer to Table 3-13, contains these status flags: • Read Disable Hold (RDH) bit is set by hardware, watchdog, and GPIO resets and sleep mode. The RDH bit indicates that all the processor’s GPIO input paths are disabled. To allow a GPIO input pin to be enabled, software must reset the RDH bit by writing a one to it.
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Clocks and Power Manager Table 3-13. PSSR Bit Definitions (Sheet 2 of 2) Clocks and Power Manager Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 4 3 2 1 0 BFS 5 SSS 6 VFS 7 PH 8 Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved Bit PSSR RDH 0x40F0_0004 0 0 0 0 0 VDD Fault Status. 0 – nVDD_FAULT pin has not been asserted since it was last cleared by a reset or the CPU.
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Clocks and Power Manager 3.5.9 Power Manager Fast Sleep Wake Up Configuration Register (PMFWR) Table 3-15. PMFWR Register Bitmap and Bit Definitions Power Manager Fast Sleep Wake Up Configuration Register (PMFWR) 8 7 6 5 4 3 2 1 FWAKE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 0 0 0 0 0 0 0 0 Reserved Bit Power Manager Reserved 0x40F0 0034 Reset 0 0 0 [31:3] 0 0 0 0 — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved.
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Clocks and Power Manager Warning: Because GPIO[89:86] were previously dedicated pins, they only reflect their PGSR value if their GPIO function is selected. Otherwise they drive their dedicated pin’s sleep state. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 3-16.
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Clocks and Power Manager 3.5.11 Reset Controller Status Register (RCSR) The CPU uses the RCSR, refer to Table 3-19, to determine what caused the last reset. The processor can be reset in four ways: • • • • GPIO reset Sleep mode Watchdog reset Hardware reset Refer to Table 2-4, “Effect of Each Type of Reset on Internal Register State” on page 2-7 for details of the behavior of different modules during each type of reset.
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Clocks and Power Manager Table 3-19. RCSR Bit Definitions Clocks and Power Manager 6 5 4 3 Reset 0 0 0 0 [31:4] 0 0 0 — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 HWR 7 WDR 8 GPR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved Bit RCSR SMR 0x40F0_0030 0 0 0 1 Reserved GPIO RESET: 3 GPR 0 – GPIO reset has not occurred since the last time the CPU or hardware reset cleared this bit.
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Clocks and Power Manager Table 3-20. Power Manager Register Locations (Sheet 2 of 2) Address 3.
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Clocks and Power Manager Table 3-21. CCCR Register Bitmap and Bit Definitions Core Clock Configuration Register (CCCR) Reset 0 0 0 [31:10] 0 0 0 0 — 0 0 0 0 7 6 0 0 N 8 0 0 0 0 0 0 0 0 0 0 0 0 1 5 4 3 1 0 0 2 1 0 0 1 L 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved Bit Clocks Manager M 0x4130 0000 0 Reserved. Read undefined and must always be written with zeroes.
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Clocks and Power Manager 3.6.2 Clock Enable Register (CKEN) CKEN enables or disables the clocks to most of the peripheral units (refer to Table 3-22). For lowest power consumption, disable any unused unit clock by clearing the appropriate bit. Table 3-22.
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Clocks and Power Manager Table 3-22.
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Clocks and Power Manager 3.6.3 Oscillator Configuration Register (OSCC) The OSCC, refer to Table 3-23, controls the 32.768-KHz oscillator configuration. It contains two bits, the set-only 32.768-KHz OON and the read-only 32.768-KHz OOK. The OON bit enables the external 32.768-KHz oscillator and can only be set by software. When the oscillator is enabled, it takes up to 10 seconds to stabilize. When the oscillator is stabilized, the processor sets the OOK bit.
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Clocks and Power Manager 3.7 Coprocessor 14: Clock and Power Management Coprocessor 14 contains two registers that control the power modes and sequences: • CP14 register 6 - CCLKCFG Register • CP14 register 7 - PWRMODE Register Table 3-25.
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Clocks and Power Manager 3.7.2 Power Mode Register (PWRMODE) Use the PWRMODE register (CP14, register 7), refer to Table 3-27, to enter idle and sleep modes. To select a mode, software writes to PWRMODE[M]. All core-initiated memory requests are completed before the clocks and power manager initiates the desired mode. Table 3-27.
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Clocks and Power Manager A 3.6864-MHz crystal must be connected between the PXTAL and PEXTAL pins. A 32.768-KHz crystal is normally connected between the TXTAL and TEXTAL pins. This configuration gives the lowest overall power consumption because the crystal’s resonant nature provides better power efficiency than an external source that drives the crystal pins. Some applications have other clock sources of the same frequency and can reduce overall cost by driving the crystal pins externally.
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System Integration Unit 4 This chapter describes the System Integration Unit (SIU) for the Intel® PXA26x Processor Family. The SIU controls several processor-wide system functions. The units contained in the SIU are: • • • • • 4.
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System Integration Unit Validate each GPIO pin’s state by reading the GPIO Pin Level Register (GPLR). You can read this register any time to confirm the state of a pin. In addition, use the GPIO Rising Edge Detect Enable Register (GRER) and GPIO Falling Edge Detect Enable Register (GFER) to detect either a rising edge or falling edge on each GPIO pin. Use the GPIO Edge Detect Status Register (GEDR) to read edge detect state. You may program these edge detects to generate interrupts (see Section 4.
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System Integration Unit 4.1.2 GPIO Alternate Functions GPIO pins are capable of having as many as six alternate functions (shown Table 4-1) that can be set to enable additional functionality within the processor. If a GPIO is used for an alternate function, then it cannot be used as a GPIO at the same time. GPIO[0] is reserved because of its special use during sleep mode and is not available for alternate functions. GPIO[15:0] are used for sleep-mode wake up.
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System Integration Unit Table 4-1.
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System Integration Unit Table 4-1.
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System Integration Unit Table 4-1.
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System Integration Unit Table 4-1.
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System Integration Unit Table 4-2.
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System Integration Unit Table 4-4.
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System Integration Unit Table 4-6.
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System Integration Unit 4.1.3.3 GPIO Pin Output Set Registers (GPSR0, GPSR1, and GPSR2) and Pin Output Clear Registers (GPCR0, GPCR1, GPCR2) When a GPIO is configured as an output, you control the state of the pin by writing to either the GPIO Pin Output Set registers (GPSR) or the GPIO Pin Output Clear registers (GPCR). An output pin is set high by writing a one to its corresponding bit within the GPSR. To clear an output pin, a one is written to the corresponding bit within the GPCR.
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System Integration Unit Table 4-11.
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System Integration Unit Table 4-14.
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System Integration Unit Note: For reserved bits in GRER2 and GFER2, writes must be zeros and reads must be ignored. Table 4-15.
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System Integration Unit Table 4-18.
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System Integration Unit 4.1.3.5 GPIO Edge Detect Status Register (GEDR) The GPIO Edge Detect Status registers (GEDR0, GEDR1, GEDR2) contain a total of 90 status bits that correspond to the 90 GPIO pins. When an edge detect occurs on a pin that matches the type of edge programmed in the GRER or GFER registers, the corresponding status bit is set in GEDR. Once a GEDR bit is set by an edge event the bit remains set until the user clears it by writing a one to the status bit.
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System Integration Unit Table 4-22.
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System Integration Unit • “00” indicates normal GPIO function for GPIO[85:0]. Indicates default dedicated functionality for GPIO[89:86]. • “01” selects alternate input function 1 (ALT_FN_1_IN) or alternate output function 1 (ALT_FN_1_OUT) for GPIO[85:0]. Selects GPIO function for GPIO[89:86].
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System Integration Unit Table 4-26.
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System Integration Unit Table 4-28.
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System Integration Unit 4.1.3.7 Example Procedure for Configuring the Alternate Function Registers In this example, GP0 is used as a generic GPIO and GP(15:1) are configured as their alternate functions. Refer to Table 4-1 for the list of alternate functions. No other GPIOs are configured. After the de-assertion of any RESET, GPDR0(15:0) configures GPIO pins in this example to be inputs. GAFR0_L(31:0) will be 0x0000_ 0000 to indicate normal GPIO function.
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System Integration Unit Table 4-30. GPIO Register Addresses (Sheet 2 of 2) 4.
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System Integration Unit 4.2.1 Interrupt Controller Operation The Interrupt Controller provides masking capability for all interrupt sources and generates either an FIQ or IRQ processor interrupt. The interrupt hierarchy of the processor is a two-level structure. • The first level identifies the interrupts from all the enabled and unmasked interrupt sources in the Interrupt Controller Mask register (ICMR).
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System Integration Unit Figure 4-2. Interrupt Controller Block Diagram All Other Qualified Interrupt Bits Interrupt Level Register (ICLR) 24 ICCR[DIM]=0 & IDLE mode=’1’ 24 FIQ Interrupt to Processor Interrupt Mask Register (ICMR) Interrupt Source Bit IRQ Interrupt to Processor Interrupt Pending Register (ICPR) IRQ Interrupt Pending Register (ICIP) FIQ Interrupt Pending Register (ICFP) 4.2.
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System Integration Unit Table 4-31 shows the bitmap of the Interrupt Controller Mask Register. Table 4-37 describes the available first-level interrupts and their location in the ICPR register. Table 4-31.
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System Integration Unit 4.2.2.3 Interrupt Controller Control Register (ICCR) The Interrupt Controller Control register (ICCR) contains a single control bit, Disable IDLE Mask (DIM). In normal IDLE mode any enabled interrupt can bring the processor out of idle mode regardless of the value in ICMR. If this bit is set, then the interrupts that can bring the processor out of IDLE mode are defined by the ICMR. Note: This register is cleared during all resets.
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System Integration Unit Table 4-34.
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System Integration Unit Table 4-36.
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System Integration Unit Table 4-36.
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System Integration Unit Table 4-36.
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System Integration Unit Table 4-37.
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System Integration Unit 4.3 Real-Time Clock (RTC) Use the RTC to configure a clock source with a wide range of frequencies. Typically, the RTC is set to be a 1 Hz output and is utilized as a system time keeper. There is also an alarm feature that enables an interrupt or a wake up event when the RTC output clock increments to a pre-set value. 4.3.1 Real-Time Clock Operation The real-time clock (RTC) provides a general-purpose real-time reference for your design.
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System Integration Unit 4.3.2.1 Real-Time Clock Trim Register (RTTR) Program the RTTR to set the frequency of the Hz clock. The reset value of this register (0x0000_7FFF) (assuming a perfect 32.768-KHz crystal) would produce an Hz-clock output of exactly 1 Hz. However, by using values other than 0x0000_7FFF, a different Hz-clock frequency is possible. Additionally, you may use a crystal that is not exactly 32.768 KHz and compensate by writing a value other than 0x0000_7FFF to the RTTR. Section 4.3.
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System Integration Unit Table 4-40. RTAR Bit Definitions Physical Address 0x4090_0004 Bit RTAR System Integration Unit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 RTMV Reset 0 0 0 0 0 0 0 Bits Name <31:0> RTMV 4.3.2.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description RTC TARGET MATCH VALUE: The value compared against the RTC counter.
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System Integration Unit They are cleared by writing ones to the AL and HZ bits. The AL and HZ bits are routed to the interrupt controller where they may be enabled to cause a first level interrupt. Write zeros to all reserved bits and ignore all reads to the reserved bits. In sleep mode, only AL events set the status bit in the RTSR register. The HZ bit is not set in sleep mode since it is a recurring event. Table 4-42 shows the bitmap of the RTC Status Register. Table 4-42.
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System Integration Unit 4.3.3.1 Oscillator Frequency Calibration To determine the value programmed into the RTTR, you must first measure the output frequency at the oscillator multiplexor (approximately 32 KHz) using an accurate time base, such as a frequency counter. This clock is externally visible by selecting the alternate function for GPIO[12] or GPIO[72]. To gain access to the clock, program this pin as an output and then switch to the alternate function. Refer to Section 4.
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System Integration Unit 4.3.3.2.2 Trim Example #2 – Measured Value Has a Fractional Component This example is more common in that the measured frequency of the oscillator has a fractional component. Again, the desired Hz-clock-output frequency is 1 Hz. If the oscillator output is measured as 32768.92 cycles/s (Hz), an integer trim is necessary so that the average number of cycles counted before generating one 1 Hz clock is 32768.92.
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System Integration Unit The trim procedure can counteract these factors by providing a highly accurate mechanism to remove the variance and shifts from the manufacturing and static environment variables on an individual system level. However, since this is a calibration solution, it is not a practical solution for dynamic changes in the system and environment and can most likely only be done in a factory setting due the equipment required. 4.3.
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System Integration Unit 4.4.2 Operating System Timer Register Definitions 4.4.2.1 Operating System Timer Match Register 0-3 (OSMR0, OSMR1, OSMR2, OSMR3) These registers are 32-bits wide and are readable and writable by the processor. They are compared against the OSCR after every rising edge of the 3.6864-MHz clock. If any of these registers match the counter register, and the appropriate interrupt enable bit is set, then the corresponding status bit in the OSSR is set.
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System Integration Unit Table 4-45.
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System Integration Unit 4.4.2.4 Operating System Timer Count Register (OSCR) The OS Timer Count register is a 32-bit counter that increments on rising edges of the 3.6864-MHz clock. This counter can be read or written at any time. It is recommended that the system writeprotect this register through the MMU protection mechanisms. After the OSCR is written, there is a delay before the register is actually updated.
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System Integration Unit Table 4-48.
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System Integration Unit 4.5 Pulse Width Modulator Use the Pulse Width Modulator (PWM) to generate as many as two signals to be output from the processor. The signals are based on the 3.6864-MHz clock and must be a minimum of 2 clock cycles wide. These signals are output from the processor by configuring the GPIOs. 4.5.1 Pulse Width Modulator Operation The processor contains two pulse width modulators: PWM0 and PWM1. Each PWM operates independently of the other, is controlled by its own set of registers.
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System Integration Unit 4.5.1.1 Interdependencies The PWM unit is clocked off the 3.6864-MHz oscillator output. Each Pulse Width Modulator Unit (PWMn) is controlled by three registers: • Pulse Width Control Register (PWM_CTRL) • Duty Cycle Control Register (PWM_DUTY) • Period Control Register (PWM_PERVAL) By setting the values in these registers the PWMn unit produces a pulse width modulated output signal. The registers contain the values for PWMn’s counters and PWMn power management mode.
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System Integration Unit 4.5.2.1 PWM Control Registers (PWM_CTRLn) The PWMn Control Register, PWM_CTRLn, contains two fields: • PRESCALE – The PRESCALE field contains the 6-bit prescale counter load value. This field allows the 3.6864-MHz-input clock PSCLK_PWMn, to be divided by values between 1 (PWM_CTL[PRESCALE] = 0) and 64 (PWM_CTL[PRESCALE] = 63). Note: The value of the divisor is one greater than the value programmed into the PRESCALE field.
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System Integration Unit The FDCYCLE bit determines whether or not PWM_OUTn is a function of the DCYCLE bits in the PWM_DUTYn register or is set high. When the FDCYCLE bit is cleared low (normal operation), the output waveform of PWM_OUTn is cyclic, with PWM_OUTn being high for the number of PSCLK_PWMn periods equal to DCYCLE. If FDCYCLE = 0x0 and DCYCLE = 0x0, PWM_OUTn is set low and does not toggle.
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System Integration Unit Note: Due to internal timing requirements, all changes to any of the PWM registers must be complete a minimum of 4 core clock cycles before the start of end of a PWM clock cycle in order to guarantee that the following PWM cycle implements the new values. Table 4-52 shows the bitmap of the PWM Period Control registers. Table 4-52.
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System Integration Unit The output waveform in Figure 4-4 is created by writing PWM_PERVALn[PV] with a decimal value of 10 (11 clocks) and PWM_DUTYn[DCYCLE] with 6. Figure 4-4 also shows that PWM_CTRLn[PRESCALE] is configured with a value of 0x0 loaded, which results in the PSCLK_PWMn having the same frequency as the 3.6864-MHz-input clock. 4.5.4 Register Summary Table 4-49 shows the registers associated with the OS timer and the physical addresses used to access them. Table 4-53.
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System Integration Unit Intel® PXA26x Processor Family Developer’s Manual 4-49
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System Integration Unit 4-50 Intel® PXA26x Processor Family Developer’s Manual
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Direct Memory Access Controller 5 This chapter describes the on-chip direct memory access (DMA) controller (DMAC) for the Intel® PXA26x Processor Family. The DMAC transfers data to and from main memory in response to requests generated by internal and external peripherals. The peripherals do not directly supply addresses and commands to the memory system. The DMAC has 16 DMA channels, 0 through 15, and every DMA request from the peripheral generates at least one memory bus cycle. 5.
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Direct Memory Access Controller Figure 5-1. DMAC Block Diagram Memory Controller System Bus (internal) Control Registers DMA Controller 16 DMA Channels Channel 15 DREQ[1:0] (external) DCSR0 Channel 0 DDADR0 DSADR0 DRCMR0 DMA_IRQ (internal) DTADR0 PREQ[37:0] (internal) DCMD0 DINT Peripheral Bus (internal) 5.1.1 Direct Memory Access Controller Channels The DMAC has 16 channels, each controlled by four 32-bit registers.
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Direct Memory Access Controller Channel information must be maintained on a per-channel basis and is contained in the DMAC registers shown in Table 5-13, “DMA Controller Registers” on page 5-28. The DMAC supports two methods of loading the DMAC registers, No-Descriptor and Descriptor Fetch Modes. The fetch modes are discussed in further detail in Section 5.1.4, “Direct Memory Access Descriptors” on page 5-6. Software must ensure cache coherency when it configures the DMA channels.
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Direct Memory Access Controller The PREQ[37:0] bits are the active high internal signals from the on-chip peripherals. Unlike DREQ[1:0], they are level sensitive. The DMAC does not sample the PREQ[37:0] signals until it completely finishes the current data transfer. For a write request to on-chip peripheral, the DMAC begins to sample the PREQ[37:0] signals after it sends the last byte of the write request.
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Direct Memory Access Controller • Set zero • Set three The pattern repeats for the next eight channel services. In each set, the channels are given roundrobin priority. Table 5-2. Channel Priority (if all channels are running concurrently) Set Channels Priority Number of times served 0 0,1,2,3 Highest 4/8 1 4,5,6,7 Higher 2/8 2 8,9,10,11 Low 1/8 3 12,13,14,15 Low 1/8 The state machine used to determine the priority of the DMA channels is shown in Table 5-3.
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Direct Memory Access Controller 5.1.4 Direct Memory Access Descriptors The DMAC operates in two distinct modes: descriptor fetch mode and no-descriptor fetch mode. The mode used is determined by the DCSRx[NODESCFETCH] bit. The descriptor fetch and no-descriptor modes can be used simultaneously on different channels. This means that some DMA channels can be active in one mode while other channels are active in the other mode. A channel must be stopped before it can be switched from one mode to the other.
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Direct Memory Access Controller Figure 5-3.
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Direct Memory Access Controller — Word [3] -> DCMDx register for the current transfer. 6. The channel waits for the request or starts the data transfer, as determined by the DCMD[FLOW] source and target bits. 7. The channel transmits a number of bytes equal to the smaller of DCMD[SIZE] and DCMD[LENGTH]. 8. The channel waits for the next request or continues with the data transfer until the DCMD[LENGTH] reaches zero. 9.
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Direct Memory Access Controller 5.1.4.3 Servicing an Interrupt If software receives an interrupt caused by a successful descriptor fetch, i.e. DCSRx[STARTINTR] = 0b1, then software must write a 1 to this bit to reset the corresponding interrupt. Software normally accomplishes this by reading the DCSRx register, modifying the data value by setting the DCSRx[STARTINTR]=0b1 and leaving the DCSRx[RUN] bit set, and then writing this modified value back to the DCSRx.
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Direct Memory Access Controller 5.1.7 Byte Transfer Order The DCMD[ENDIAN] bit indicates the byte ordering in a word when data is read from or written to memory. Refer to Figure 5-5 on page 5-10 for details. The DCMD[ENDIAN} bit must be set to 0, which is little endian transfers. Figure 5-5, “Little Endian Transfers” on page 5-10 shows the order which data is transferred as determined by the DCMD[ENDIAN] and DCMD[SIZE] bits.
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Direct Memory Access Controller 5.1.8 Trailing Bytes The DMAC normally transfers bytes equal to the transaction size specified by DCMD[SIZE]. As the descriptor nears the end its data, the number of trailing bytes in the DCMD[LENGTH] field may be smaller than the transfer size. The DMA can transfer the exact number of trailing bytes if the DCMD[FLOWSRC] and DCMD[FLOWTRG] bits are both 0 or if it receives a corresponding request from a peripheral or companion chip.
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Direct Memory Access Controller 5.2.1 Servicing Internal Peripherals The DMAC provides the DMA Request to Channel Map Registers (DRCMRx) that contain four bits used to assign a channel number for each possible DMA request. An internal peripheral can be mapped to any of the 16 available channels. See Table 5-5, “DMA Quick Reference for Internal Peripherals” on page 5-13 to configure the internal peripherals for DMA accesses.
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Direct Memory Access Controller 1. The DMAC transfers the required number of bytes from the I/O device addressed by DSADRx[31:0] to the DMAC write buffer. 2. The DMAC transfers the data to the memory controller via the internal bus. DCMD[WIDTH] specifies the width of the internal peripheral to which the transfer is being made. 3. At the end of the transfer, DTADRx is increased by the smaller value of DCMDx[LENGTH] and DCMD[SIZE]. DCMDx[LENGTH] is decreased by the same number.
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Direct Memory Access Controller Table 5-5. DMA Quick Reference for Internal Peripherals (Sheet 2 of 2) Unit FIFO Address Width (bytes) DCMD.
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Direct Memory Access Controller DREQ[1:0]. The DREQ signal can be mapped to one of the 16 available channels. The DREQ signals are sampled on every peripheral clock (PCLK) and if any of the DREQ signals are sampled non-zero, a lookup is performed on the corresponding bits in the DRCMRx. This allows requests to one of the channels to be mapped. If the external peripheral address is in the DSADR, the DCMDx[FLOWSRC] bit must be set to a 1.
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Direct Memory Access Controller 3. At the end of the transfer, DTADRx is increased by the smaller value of DCMDx[LENGTH] and DCMD[SIZE]. DCMDx[LENGTH] is decreased by the same number. Note: The process shown for a flow-through DMA write to an external peripheral indicates that the external address increases. Some external peripherals, such as FIFOs, do not require an increment in the external address.
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Direct Memory Access Controller • • • • • 5.3 DCMD[INCSRCADDR] = 1 DCMD[INCTRGADDR] = 1 DCMD[FLOWSRC] = 0 DCMD[FLOWTRG] = 0 DCSR[RUN] =1 Direct Memory Access Controller Registers The section describes the Direct Memory Access Controller registers. 5.3.1 DMA Interrupt Register The read-only DMA Interrupt Register (DINT) (Figure 5-6) logs the interrupts for each channel.
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Direct Memory Access Controller Table 5-7.
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Direct Memory Access Controller Table 5-7.
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Direct Memory Access Controller Table 5-8. DRCMRx Registers Bitmap Bit Definitions DMA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RESERVED Reset 0 0 0 0 0 0 0 Bits Name 31:8 — 0 0 0 0 0 0 0 7 6 MAPVLD Bit DMA Request to Channel Map Register (DRCMRx) 0 0 0 0 0 0 0 0 0 0 0 5 4 3 RESERVED Physical Address 0x4000_0100 - 0x4000_019C 0 0 2 1 0 CHLNUM 0 0 0 0 0 Description Reserved – Read as unknown and must be written as zero.
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Direct Memory Access Controller Table 5-9. DMA Descriptor Address Register Bit Definitions 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 DMAC 8 DESCRIPTOR ADDRESS Reset 7 6 5 4 3 2 1 RESERVED Bit DMA Descriptor Address Register (DDADRx) Uninitialized Bits 31:4 3:1 Name 0 STOP 0x4000_02x0 0 Description DESCRIPTOR Address of next descriptor (read / write). ADDRESS — Reserved – Read as unknown and must be written as zero. STOP (read / write): 0 – Run channel.
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Direct Memory Access Controller Table 5-10. DSADRx Register Bitmap Bit Definitions 0x4000_02x4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 DMAC 8 7 6 5 4 3 2 1 SOURCE ADDRESS Reset 0 RESERVED Bit DMA Source Addr Register (DSADRx) Uninitialized Bits Name 31:3 SRCADDR Description SOURCE ADDRESS (read / write): Address of the internal peripheral or address of a memory location.
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Direct Memory Access Controller Table 5-11.
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Direct Memory Access Controller Table 5-12.
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Direct Memory Access Controller Table 5-12.
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Direct Memory Access Controller Example 5-1. How to set up and start a channel: The following example shows how to set up a channel to transfer LENGTH words from the address DSADR to the I/O address DTADR. The example also shows how to start the transfer. The example sets the stop bit in the DDADR, so the DMA channel stops after it completely transfers LENGTH bytes of data. // build real descriptor desc[0].ddadr = STOP; desc[0].dsadr = DSADR; desc[0].dtadr = DTADR; desc[0].
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Direct Memory Access Controller 7. Program the channel’s DDADR with the descriptor created in Step 5. 8. Set the DCSR[RUN] to a 1. Example 5-4. How to initialize a channel that is going to be used by a direct DMA master: The most efficient way to move data between an I/O device and main memory is the processor’s descriptor-based DMA system. Each application has different requirements, so a descriptor-based DMA may be best for some applications while a non-descriptor-based DMA is best for others.
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Direct Memory Access Controller 5.5 Direct Memory Access Controller Registers Locations This section lists the addresses of the Direct Memory Access Controller registers. Refer to Table 5-13. Table 5-13.
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Direct Memory Access Controller Table 5-13.
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Direct Memory Access Controller Table 5-13.
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Direct Memory Access Controller Table 5-13.
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Direct Memory Access Controller 5-32 Intel® PXA26x Processor Family Developer’s Manual
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Memory Controller 6 This chapter describes the external memory interface structures and memory-related registers supported by the Intel® PXA26x Processor Family. The PXA26x processor family adds support for the extended mode register used in low-power SDRAM. It also adds support for 8 bit read transactions from PCMCIA and static memory. 6.
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Memory Controller Figure 6-1.
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Memory Controller partition pairs: the 0/1 pair and the 2/3 pair. The partitions in a pair must be identical in size and configuration. The two pairs may be different (for example, the 0/1 pair can be 100-MHz SDRAM on a 32-bit data bus, while the 2/3 pair can be 50-MHz SDRAM on a 16-bit data bus). The processor SDRAM Controller includes these signals: • • • • • • • • • 4 partition selects (nSDCS[3:0]) 4 byte selects (DQM[3:0]).
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Memory Controller The VLIO interface differs from SRAM in that it allows the data-ready input signal, RDY, to insert a variable number of wait states. For all static memory types, each chip select can be individually configured to a 16-bit or 32-bit-wide data bus. nOE is asserted on all reads, nPWE is asserted on writes to VLIO devices, and nWE is asserted on writes to all other static devices, both synchronous and asynchronous. For SRAM and VLIO, DQM[3:0] are byte selects for both reads and writes.
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Memory Controller Figure 6-2.
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Memory Controller Figure 6-3. Asynchronous Static Memory System Example nCS(2:0) nSDRAS, nSDCAS, nWE, CKE(0) SDCLK(0) MA(22:2) 2Mx16 SMROM 0 0 1 15:0 1 nCS SRAM 2 nCS nCS nRAS nRAS nCAS nCAS nOE nMR nMR nWE CKE CKE CLK CLK addr(12:0) 22:10 2Mx16 SMROM addr(12:0) 22:10 22:2 addr(20:0) DQML 0 DQML 0 DQML DQMH 1 DQMH 1 DQMH DQ(15:0) 15:0 DQ(15:0) 15:0 DQ(15:0) MD(31:0) nOE DQM[3:0] 2Mx16 SMROM 0 2Mx16 SMROM 1 nCS 2 3 31:16 6.
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Memory Controller Table 6-1 lists all the transactions that the processor can generate. No burst can cross an aligned 32byte boundary. On a 16-bit data bus, each full word access becomes a two half-word burst, with address bit 1 set to a 0. Each write access to flash memory space must take place in one non-burst operation, regardless of the bus size. Table 6-1. Device Transactions Bus Operation 6.4.
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Memory Controller If memory does not occupy all 64 MB of the partition, reads and writes from or to the unoccupied portion are processed as if the memory occupies the entire 64 MB of the memory partition. A single word (or half-word if the data bus width is defined as 16-bits) access to a disabled SDRAM partition (MDCNFG:DEx=0) causes a CBR refresh cycle to all four partitions. This technique is used in the hardware initialization procedure.
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Memory Controller 6.6 Synchronous DRAM Memory Interface Each possible SDRAM portion of the Memory Map is referred to as a partition, to distinguish them from banks internal to SDRAM devices. The signals used to control the SDRAM memory are listed in Section 6.2.1, “SDRAM Interface Overview”. 6.6.1 SDRAM MDCNFG Register MDCNFG is a read/write register and contains control bits for configuring the SDRAM.
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Memory Controller Table 6-3.
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Memory Controller Table 6-3.
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Memory Controller 6.6.2 SDRAM Mode Register Set Configuration Register The MDMRS register issues an Mode Register Set (MRS) command to the SDRAM. The value written in this register is placed directly on address lines MA[24:17] during the MRS command. For MA[16:10], values which are fixed or derived from the MDCNFG register are placed on the address bus. When setting the values to be written out on the address lines, base the values on the addressing mode being used.
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Memory Controller Table 6-4. MDMRS Register Bitmap (Sheet 2 of 2) Reset processor 0 6.6.2.1 0 0 0 0 0 6:4 MDCL0 3 MDADD0 2:0 MDBL0 0 0 0 1 0 0 0 1 0 0 7 6 0 0 0 0 0 0 0 4 3 0 0 MDCL0 5 0 0 1 2 1 0 MDBL0 8 MDMRS0 Reserved MDBL2 MDCL2 MDMRS2 0 MDADD2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved Bit MDMRS MDADD0 0x4800 0040 0 1 0 SDRAM PARTITION PAIR 0 CAS LATENCY – derived from MDCNFG:DTC0. Writes are ignored.
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Memory Controller Table 6-5.
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Memory Controller Refer to Table 6-6. Table 6-6.
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Memory Controller Table 6-6.
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Memory Controller Table 6-6.
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Memory Controller • • • • • SDRAM timing category Data-bus width Number of row, column, and bank address bits Addressing scheme Data-latching scheme Table 6-7, “Sample SDRAM Memory Size Options” on page 6-18 shows a sample of the supported SDRAM configurations. Table 6-7.
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Memory Controller Table 6-4 shows how the SDRAM row and column addresses are mapped to the internal SDRAM address. The SDRAM row and column addresses are muxed. The SDRAM row is sent during an Active command and is followed by the column address during the read or write command. MA<20> is driven with 0 during column addressing. BA[1:0] tells the SDRAM which bank is being read from and remains stable during column addressing.
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Memory Controller Table 6-8.
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Memory Controller Table 6-9.
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Memory Controller Table 6-9.
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Memory Controller Table 6-10. Pin Mapping to SDRAM Devices with Normal Bank Addressing (Sheet 2 of 3) Pin mapping to SDRAM devices for Normal Addressing. MA[24:10] represent the address signals driven from the processor.
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Memory Controller Table 6-10. Pin Mapping to SDRAM Devices with Normal Bank Addressing (Sheet 3 of 3) Pin mapping to SDRAM devices for Normal Addressing. MA[24:10] represent the address signals driven from the processor. # Bits Bank x Row x Col x Data 2x13x10x16 MA24 MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 2x13x11x32 NOT VALID (too big) 2x13x11x16 NOT VALID (too big) A5 A4 A3 A2 A1 A0 Table 6-11.
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Memory Controller Table 6-11. Pin Mapping to SDRAM Devices with SA-1111 Addressing (Sheet 2 of 2) Pin mapping to SDRAM devices for SA1111 Addressing Options. MA[24:10] represent the address signals driven from the PXA26x processor family.
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Memory Controller • • • • Power-Down (PWRDN) Enter Self-Refresh (SLFRSH) Exit Power-Down (PWRDNX) No Operation (NOP) Table 6-12 shows the SDRAM interface commands. The table assumes the bank bits for the SDRAM are sent out on external address lines MA<24:23>. Table 6-12.
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Memory Controller 6.6.6 SDRAM Waveforms Additional waveforms for the SDRAM controller are shown in Figure 6-5, Figure 6-6, Figure 6-7, Figure 6-8, Figure 6-9, Figure 6-10. Figure 6-5. SDRAM Read 0ns 50ns tRP 100ns tRCD 150ns 200ns CL SDCLK nSDCS MA[24:0] bank row col nSDRAS nSDCAS nWE DATA 0 DQM[3:0] 1 2 3 0000 tRP = 2 clks tRAS = 2 clks tRCD = 2 clks CL = 2 clks Figure 6-6.
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Memory Controller Figure 6-7. SDRAM Read With a Second Read to Same Bank, Different Row 0ns 50ns 100ns 150ns tRP = 2 clks tRAS = 7 clks tRCD = 2 clks CL = 2 clks tRAS tRCD CL tRP tRCD CL SDCLK nSDCS MA[24:0] row bank col row col nSDRAS nSDCAS nWE DATA 0 DQM[3:0] 1 2 4 3 5 6 7 0000 0000 Figure 6-8.
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Memory Controller Figure 6-9. SDRAM Write 0ns 25ns 50ns 75ns tRP = 2 clks tRCD = 2 clks tRAS = 2 clks CL = 2 clks tRCD CL SDCLK nSDCS MA[24:0] row col nSDRAS nSDCAS nWE DATA DQM[3:0] 0 1 2 3 mask0 mask1 mask2 mask3 Figure 6-10.
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Memory Controller 6.7 Synchronous Static Memory Interface The synchronous static memory interface supports SMROM and non-SDRAM-like flash memories. The synchronous static memory can be configured for any of the nCS[3:0] signals. Chip Select 0 must be used for boot memory. Synchronous static memories in bank pairs 1/0 or 3/2 must be set to the same timing. If any of the nCS[3:0] banks are configured for Synchronous Static Memory via SXCNFG[SXENx], the corresponding half-words of MSC0 (see Section 6.8.
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Memory Controller Table 6-14.
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Memory Controller Table 6-14.
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Memory Controller Table 6-14.
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Memory Controller Table 6-14.
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Memory Controller Table 6-14.
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Memory Controller Table 6-16.
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Memory Controller Table 6-17. SXMRS Register Bitmap Reset 6.7.
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Memory Controller Figure 6-11. SMROM Read Timing Diagram Half-Memory Clock Frequency, 0ns 50ns 100ns RL = 2 150ns CL = 5 SDCLK SDCKE command NOP ACT NOP READ NOP STOP NOP nCS[0] nSDRAS nSDCAS MA[24:10] row col nWE nOE d0 MD DQM[3:0] d1 d2 0000 RDnWR 6.7.4 Non-SDRAM Timing SXMEM Operation Non-SDRAM timing synchronous flash operation resets to asynchronous mode (page-mode for reads and asynchronous single word writes).
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Memory Controller Table 6-18. Read Configuration Register Programming Values Bits Field Name Value to Program 2:0 BURST LENGTH 5:3 RESERVED 6 CLOCK CONFIGURATION 7 BURST SEQUENCE 010 8 Word Burst 000 1 Use rising edge of clock 1 Linear burst Order (INTEL BURST ORDER IS NOT SUPPORTED) N/A 8 WAIT CONFIGURATION 9 DATA OUTPUT CONFIGURATION 10 RESERVED nWAIT from the flash device is ignored by the processor.
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Memory Controller Table 6-19. Frequency Code Configuration Values Based on Clock Speed (Sheet 2 of 2) MEMCLK Frequency 6.7.4.1 SDCLK0 Frequency 133 66 147 Not supported 166 Not supported Valid Frequency Configurations MDREFR: K0DB2 1 5/6 Corresponding CAS Latencies 6/7 Non-SDRAM Timing Flash Read Timing Diagram The burst-of-eight read timing diagram is shown in Figure 6-12. Figure 6-12.
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Memory Controller • nADV assert time = 3 MEMCLKs • MA, nCS setup to nADV asserted = 1 MEMCLK • nADV deasserted to nOE asserted = (Code * 2) – 4 MEMCLKs 6.8 Asynchronous Static Memory 6.8.1 Static Memory Interface The Static Memory interface is made up of six chip selects: nCS[5:0].
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Memory Controller Table 6-20. 32-Bit Bus Write Access (Sheet 2 of 2) Data Size MA[1:0] DQM[3:0] 16 bit 00 1100 16 bit 10 0011 32 bit 00 0000 Table 6-21.
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Memory Controller Table 6-22. 32-Bit Byte Address Bits MA[1:0] for Reads Based on DQM[3:0] DQM[3:0] MA[1:0] 0000 00 0001 1101 1001 0101 01 1011 0011 10 0111 11 Anything Else 00 Table 6-23. 16-Bit Byte Address Bit MA[0] for Reads Based on DQM[1:0] DQM[1:0] MA[0] 00 0 10 0 01 1 11 0 Table 6-24.
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Memory Controller 6.8.2 Asynchronous Static Memory Control Registers (MSC0 – 2) The MSC0, MSC1, and MSC2 are read/write registers and contain control bits for configuring Static Memory (or Variable Latency I/O) that correspond to chip-select pairs nCS(1:0), nCS(3:2), and nCS(5:4), respectively. Timing fields are specified as numbers of memory clock cycles. Each of the three registers contain two identical CNFG fields One for each chip select in the pair.
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Memory Controller Table 6-25.
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Memory Controller Table 6-25.
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Memory Controller Table 6-25.
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Memory Controller Table 6-26. Asynchronous Static Memory and Variable Latency I/O Capabilities (Sheet 2 of 2) Timing (Memory Clocks) MSCx[RTx] Burst-of-4 010 ROM or Flash (non-burst writes) 100 6.8.
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Memory Controller Figure 6-14.
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Memory Controller Figure 6-15.
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Memory Controller Figure 6-16. 32-Bit Non-burst ROM, SRAM, or Flash Read Timing Diagram - Four Data Beats (MSC0:RDF = 4, MSC0:RRR = 1) MEMCLK nCS[0] RDF+2 RDF+1 0 1 RDF+1 MA[25:2] MA[1:0] 2 3 00 RDF+1 RRR*2+1 RDF+1 nADV(nSDCAS) nOE nWE RDnWR MD[31:0] DQM[3:0] 0000 nCS[1] 6.8.4 SRAM Interface Overview The processor provides a 16-bit or 32-bit asynchronous SRAM interface that uses the DQM pins for byte selects on writes. nCS[5:0] select the SRAM bank.
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Memory Controller For writes to SRAM, if all byte enables are turned off (masking out the data, DQM = 1111), then the write enable are 1 (nWE = 1) for this write beat. This can result in a period when nCS is asserted, but neither nOE nor nWE is asserted. This happens with a write of 1 beat to SRAM, but all byte enables are turned off. Figure 6-17 shows the timing for SRAM writes. Figure 6-17.
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Memory Controller • tAH = Address hold after nWE deasserted = 1 MEMCLK • nWE high time between burst beats = 2 MEMCLKs 6.8.5 Variable Latency I/O (VLIO) Interface Overview VLIO read accesses differ from SRAM read accesses in that the nOE toggles for each beat of a burst. The first nOE assertion occurs two memory cycles after the assertion of the chip select nCS. Also, for Variable Latency I/O writes, nPWE is used instead of nWE so SDRAM refreshes can be executed while performing the VLIO transfers.
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Memory Controller Figure 6-18.
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Memory Controller Figure 6-19.
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Memory Controller 6.8.6 FLASH Memory Interface The processor provides an SRAM-like interface for access of flash memory. The RDF fields in the MSCx registers are the latency for each read access to non-burst flash, or the first read access to burst flash. The RDF fields also control the nWE low time during a write cycle to flash. The RDN field controls subsequent read access times to burst flash and the nWE low time during a write cycle to non-burst flash.
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Memory Controller Figure 6-20. Asynchronous 32-Bit Flash Write Timing Diagram (2 Writes) MEMCLK RRR*2+1 nCS[0] tAS MA[25:2] A0 A1 MA[1:0] byte addr byte addr tCES tASW tCEH tAH RDF+1 RD RD RDF+1 nWE nOE RDnWR tDH tDSWH MD[31:0] CMD DATA DQM[3:0] mask mask nADV(nSDCAS) In Figure 6-20 some of the parameters are defined as follows: • • • • • • • 6.
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Memory Controller 6.9.1 Expansion Memory Timing Configuration Register MCMEM0, MCMEM1, MCATT0, MCATT1, MCIO0, and MCIO1 are read/write registers that contain control bits for configuring the timing of the 16-bit PC Card/Compact Flash interface. The programming of each of the four fields in each of the six registers lets software to individually select the duration of accesses to I/O, common memory, and attribute space for each of two 16-bit PC Card/Compact Flash card slots.
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Memory Controller Table 6-28. MCATTx Register Bitmap 13:12 — Reserved 11:7 MCATTx_ ASST Code for the command assertion time – See Table 6-30 for a description of this code and its affects on the command assertion. 6:0 MCATTx_ SET Minimum Number of memory clocks to set up address before command assertion for MCATT for socket x is equal to MCATTx_SET + 2. Table 6-29.
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Memory Controller Table 6-30.
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Memory Controller 6.9.2 Expansion Memory Configuration Register (MECR) To eliminate external hardware, two bits, shown in Table 6-31, are used to signal the memory controller when a card (16-Bit PC Card/Compact Flash) is inserted in the socket and the number of cards supported in the system. The number-of-sockets bit is required because the PSKTSEL pin is used as the nOE for the data transceivers in single socket mode.
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Memory Controller Figure 6-24. 16-Bit PC Card Memory Map Socket 1 Common Memory Space 0x3C00 0000 Socket 1 Attribute Memory Space 0x3800 0000 Reserved 0x3400 0000 Socket 1 I/O Space 0x3000 0000 Socket 0 Common Memory Space 0x2C00 0000 0x2800 0000 Socket 0 Attribute Memory Space Reserved 0x2400 0000 Socket 0 I/O Space 0x2000 0000 The 16-bit PC Card Memory Map space is divided into eight partitions, four for each card slot.
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Memory Controller Table 6-32. Common Memory Space Write Commands nPCE2 nPCE1 MA<0> nPOE nPWE MD[15:8] MD[7:0] 0 0 0 1 0 Odd Byte Even Byte 1 0 0 1 0 Unimportant Even Byte 1 0 1 1 0 Unimportant Odd Byte Table 6-33. Common Memory Space Read Commands nPCE2 nPCE1 MA<0> nPOE nPWE MD[15:8] MD[7:0] 0 0 0 0 1 Odd Byte Even Byte 1 0 0 0 1 Unimportant Even Byte 1 0 1 0 1 Unimportant Odd Byte Table 6-34.
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Memory Controller Table 6-38. 8-Bit I/O Space Write Commands (nIOIS16 = 1) nPCE2 nPCE1 MA<0> nPIOR nPIOW MD[15:8] MD[7:0] 1 0 0 1 0 Unimportant Even Byte 1 0 1 1 0 Unimportant Odd Byte Table 6-39. 8-Bit I/O Space Read Commands (nIOIS16 = 1) nPCE2 nPCE1 MA<0> nPIOR nPIOW 6.9.
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Memory Controller Figure 6-25. Expansion Card External Logic for a One-Socket Configuration PXA26x Processor Family Socket 0 MD<15:0> D<15:0> DIR nOE RD/nWR GPIO nPCD0 GPIO nPCD1 nCD<2> PRDY_BSY0 PADDR_EN0 RDY/nBSY nCD<1> PSKTSEL GPIO GPIO MA[25:0] A[25:0] nWE nPWE nREG nPREG nCE<2:1> nOE nIOR nIOW nPCE<2:1> nPOE nPIOR nPIOW 5V to 3.3V or 2.5V nWAIT nPWAIT 5V to 3.3V or 2.5V nIOIS16 nIOIS16 Figure 6-26 shows the glue logic need for a two-socket system.
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Memory Controller Figure 6-26.
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Memory Controller 6.9.5 Expansion Card Interface Timing Diagrams and Parameters Figure 6-27 shows a 16-bit access to a 16-bit memory or I/O device. When common memory is accessed, the MCMEM0 and MCMEM1 registers are used, depending on whether card socket 0 or 1 is addressed. MCIO0 and MCIO1 are used for I/O accesses and MCATT0 and MCATT1 are used for access to attribute memory. Figure 6-27.
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Memory Controller Figure 6-28. 16-Bit PC Card I/O 16-Bit Access to 8-Bit Device 0ns 100ns 200ns 300ns memclk MA[25:1],nPREG,PSKTSEL MA[0] nPCE2 nPCE1 IOx_SET IOx_SET IOx_HOLD IOx_HOLD nPIOW,nPIOR RDnWR nIOIS16 IOx_ASST_HOLD IOx_ASST_HOLD IOx_ASST_WAIT + wait states IOx_ASST_WAIT + wait states nPWAIT read_data write_data Low Byte High Byte The interface waits the smallest possible amount of time (x_ASST_WAIT) before it checks the value of the nPWAIT signal.
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Memory Controller Figure 6-29. Alternate Bus Master Mode EXTERNAL SYSTEM PXA26x Processor Family SDCKE<1> SDCLK<1> nSDCS(0) nSDRAS Memory Controller nSDCAS nWE External SDRAM Bank 0 MA[25:0] DQM[3:0] MBGNT MBREQ MD[31:0] Companion Chip GPIO Block GPIO<13> (MBGNT) GPIO<14> (MBREQ) Figure 6-30.
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Memory Controller 6.10.1 Alternate Bus Master Mode The processor supports the presence of an alternate master on the SDRAM memory bus. The alternate master is given control of the bus with a hardware handshake that is performed through MBREQ and MBGNT, which are invoked through the alternate functions on GPIO<14> and GPIO<13>, respectively. The memory controller performs an SDRAM refresh if SDRAM clocks and clock enable are turned on.
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Memory Controller 7. The memory controller performs an SDRAM refresh if SDRAM clocks and clock enable are turned on. 8. The memory controller sends an MRS command to the SDRAMs if the MDCNFG:SA1111x bit is enabled. This changes the SDRAM burst length back to four. If the refresh counter for the processor requested a refresh cycle during the alternate master’s tenure, a refresh cycle runs first, followed by any other bus transactions that stalled during that period.
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Memory Controller is deasserted or, as part of the sleep entry routine, the alternate master can be disabled. If necessary, the alternate master can hold the bus until its transaction is completed. After the memory controller has completed all outstanding transactions, it places SDRAM into self-refresh and allows the processor to complete the sleep entry sequence. Note: The alternate bus master must de-assert MBREQ when nVDD_FAULT or nBATT_FAULT is asserted. 6.
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Memory Controller 6.11.2.2 Boot-Time Configurations The boot time configurations are shown in Figure 6-31 – Figure 6-33. A boot from a single 32Mbit SMROM with nWORD = 1 is not supported. For the PXA260, BOOT_SEL[2:0] must be set appropriately for the boot ROM. For the PXA261 and PXA262, BOOT_SEL[2:0] must be 0b001. For the PXA263, BOOT_SEL[2:0] must be 0b000. Three Configuration registers are affected at reset – MSC0:RBW0, MDREFR:E0PIN/K0RUN, and SXCNFG. Figure 6-31.
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Memory Controller Figure 6-32.
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Memory Controller Figure 6-33.
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Memory Controller Table 6-41.
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Memory Controller being configured, the SDRAM banks must be disabled and MDREFR:APD must be deasserted (auto-power-down disabled). a. Write SXCNFG (with enable bits asserted). b. Write to SXMRS to trigger an MRS command to all enabled banks of synchronous static memory. c. SXLCR must only be written when it is required by the SDRAM-like synchronous flash device for command encoding. 3. In systems that contain SDRAM, transition the SDRAM controller through this state sequence: a.
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Memory Controller 11. Optionally, in systems that contain SDRAM or synchronous static memory, enable autopower-down by setting MDREFR:APD. 6.13 General Purpose Input/Output Reset Procedure On a GPIO Reset, the Memory Controller registers keep the values they had before the reset. No new configuration programming is required. However, SDRAM refreshes do not occur during the reset time. After nRESET_OUT is deasserted, the memory controller will continue refreshing.
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Liquid Crystal Display Controller 7 The liquid crystal display (LCD) controller provides an interface from the Intel® PXA26x Processor Family to a passive (DSTN) or active (TFT) flat panel display. Monochrome and several color pixel formats are supported (see Section 7.1.1, “Features” on page 7-2). This chapter covers these topics: • • • • • • 7.1 Section 7.1, “Overview” Section 7.2, “Liquid Crystal Display Controller Operation” Section 7.3, “Detailed Module Descriptions” Section 7.
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Liquid Crystal Display Controller from the dither logic is grouped into the selected format (e.g., 8-bit color, dual panel, 16-bit color., etc.) and placed in a FIFO buffer before being sent out on the LCD controller’s pins and driven to the display using the pixel clock. Depending on the type of panel used, the LCD controller is programmed to use either 4-, 8-, or 16pixel data output pins. Single-panel monochrome displays use either four or eight data pins to send 4 or 8 pixels for each pixel clock.
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Liquid Crystal Display Controller Figure 7-1.
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Liquid Crystal Display Controller 7.1.2 Pin Descriptions When the LCD controller is enabled, all of the LCD pins are outputs only. When the LCD controller is disabled, its pins are available for general-purpose input/output (GPIO). Refer to Section 4, “System Integration Unit” for details. Table 7-1 describes the LCD controller’s pins. For more detailed information, see Section 7.3.5, “Liquid Crystal Display Controller Pin Usage”. All of the LCD pins are outputs only. Table 7-1.
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Liquid Crystal Display Controller • Program all of the LCD configuration registers except the Frame Descriptor Address registers (FDADRx) and the LCD Controller Configuration Register 0 (LCCR0). See Section 7.6 for details of all registers. • Program FDADRx with the memory address of the palette/frame descriptor, as described in Section 7.6.5.2. • Enable the LCD controller by writing to LCCR0, as described in Section 7.6.1. For more information, see Section 7.6.1.14, “LCD Enable (ENB)”.
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Liquid Crystal Display Controller • • • • 7.3.1 Section 7.3.3, “Temporal Modulated Energy Distribution (TMED) Dithering” Section 7.3.4, “Output FIFOs” Section 7.3.5, “Liquid Crystal Display Controller Pin Usage” Section 7.3.6, “Direct Memory Access” Input FIFOs Data fetched from external memory by the dedicated DMAC is placed in one of two input FIFO buffers. Each input FIFO comprises 128 bytes, organized as 16 entries by 8 bytes.
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Liquid Crystal Display Controller Figure 7-2. Temporal Dithering Concept - Single Color Time (frame #) Color Code 8 bits X position Y position 1 bit Temporal Modulator Low Pass Filter (Panel) EYE This dithering concept is applied separately to each color displayed. Each color has zeros added to make the data for each color 8 bits. If a monochrome display is used, only a single matrix (blue) is used.
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Liquid Crystal Display Controller 1. The new CV is sent through the color offset adjuster, where it is used as a lookup into the matrix selected by TCR[COAM]. 2. Either the 8-bit output of the chosen matrix or 00h, as selected by TCR[COAE], is added to the appropriate color’s seed register value in register TRGBR to form an offset. 3. This offset is added to the result of the multiplication of the frame number and the CV to form the algorithm’s lower boundary (only the lower 8 bits are used). 4.
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Liquid Crystal Display Controller 7.3.4 Output FIFOs The LCD controller has two output FIFOs to queue pixel data before it is sent to the pins. Each output FIFO is 16 bytes, organized as 16 entries by 8-bits wide. Pixel values are accumulated in a serial shifter and written to the FIFO buffers in 4-, 8-, or 16-bit quantities.
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Liquid Crystal Display Controller 7.3.5.2 Active-Display Timing In active display mode (LCCR0[PAS]=1), L_PCLK toggles continuously as long as the LCD controller is enabled. The other pins function as: L_BIAS – Output enable. When asserted, the LCD latches L_DD data using L_PCLK. L_LCLK – Horizontal synchronization signal (HSYNC) L_FCLK – Vertical synchronization signal (VSYNC) If an output FIFO underrun occurs, the data on the L_DD pins is repeated, L_BIAS stays asserted, and L_PCLK keeps running.
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Liquid Crystal Display Controller 7.4 Liquid Crystal Display External Palette and Frame Buffers The LCD controller supports a variety of user-programmable options, including display type and size, frame buffer location, encoded pixel size, and output data width. Although all programmable combinations are possible, the displays available on the market dictate which combinations of these programmable options are practical.
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Liquid Crystal Display Controller Figure 7-5.
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Liquid Crystal Display Controller Bit 31 30 29 28 ... 3 2 1 0 Base + 0x0 Pixel 31 Pixel 30 Pixel 29 Pixel 28 ... Pixel 3 Pixel 2 Pixel 1 Pixel 0 Base + 0x4 Pixel 63 Pixel 62 Pixel 61 Pixel 60 ... Pixel 35 Pixel 34 Pixel 33 Pixel 32 Figure 7-7. 2-Bits Per Pixel Data Memory Organization Bit 1 2 bits/pixel Bit 31 30 29 0 Palette Buffer Index<1:0> 28 27 26 ... 7 6 5 4 3 2 1 0 Base + 0x0 Pixel 15 Pixel 14 Pixel 13 ...
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Liquid Crystal Display Controller Bit Note: 31 16 15 0 Base + 0x0 Pixel 1 Pixel 0 Base + 0x4 Pixel 3 Pixel 2 For passive 16 bits per pixel operation, the Raw Pixel Data must be organized as shown above. ) Figure 7-11.
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Liquid Crystal Display Controller If dummy pixels are to be inserted, the panel must ignore the extra pixel clocks at the end of each line that correspond to the dummy pixels. Use the following equation to calculate the total size of the frame buffer (in bytes). This calculation encodes the length of the frame buffer in the DMA descriptors (Section 7.6.5.5.4, “Transfer Length (LEN)” on page 7-41). The first term is the size required for the encoded pixel values.
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Liquid Crystal Display Controller Figure 7-12.
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Liquid Crystal Display Controller Figure 7-13.
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Liquid Crystal Display Controller Figure 7-15.
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Liquid Crystal Display Controller Figure 7-16. Active Mode Pixel Clock and Data Pin Timing L_FCLK (VSYNC) L_LCLK (HSYNC) L_BIAS (OE) PCP = 0 L_PCLK LDD[15:0] Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel 4 PCP - Pixel Clock Polarity 0 - Pixels sampled from data pins on rising edge of clock. 1 - Pixels sampled from data pins on falling edge of clock. For PCP = 1 the L_PCLK waveform is inverted, but the timing is identical. 7.
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Liquid Crystal Display Controller An additional control field exists to tune the DMAC’s performance based on the type of memory system implemented with the processor. This field controls the placement of a minimum delay between each LCD-DMA-request-during-palette loads to insure enough bus bandwidth is given to other bus masters accesses. The DMA descriptor addresses are initially programmed by software. After that, the other DMA registers are programmed by the hardware. Section 7.6.
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Liquid Crystal Display Controller Table 7-2.
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Liquid Crystal Display Controller Table 7-2.
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Liquid Crystal Display Controller After a word of palette data is written to the input FIFO, the value contained within PDD is loaded to a down counter. The down counter disables the palette from issuing another DMA request until the counter decrements to zero. This counter ensures that the LCD’s DMAC does not tie up the full bandwidth of the processor system bus. Once the counter reaches zero, any pending or future DMA requests by the palette cause the DMAC to arbitrate for the bus.
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Liquid Crystal Display Controller When PAS=1, active mode is selected. 1- and 2-bit pixel modes are not supported in active mode. For 4- and 8-bit pixel modes, pixel data is transferred via DMA from off-chip memory to the input FIFO, unpacked, and used to select an entry from the palette, just as in passive mode. However, the value read from the palette bypasses the LCD controller’s dither logic and is sent directly to the output FIFO to be driven onto the LCD’s data pins.
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Liquid Crystal Display Controller Figure 7-17. Frame Buffer/Palette Output to LCD Data Pins in Active Mode 4/8/16 Bits/Pixel Mode, Frame Buffer or Palette Entry 7.6.1.
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Liquid Crystal Display Controller 7.6.1.12 Single-/Dual-Panel Select (SDS) In passive mode (PAS=0), the single-/dual-panel select (SDS) bit selects the type of display control implemented by the LCD screen. When SDS=0, single-panel operation is selected (pixels presented to screen a line at a time). When SDS=1, dual-panel operation is selected (pixels presented to screen two lines at a time). Single-panel LCD drivers have one line/row shifter and driver for pixels and one line pointer.
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Liquid Crystal Display Controller Figure 7-18.
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Liquid Crystal Display Controller blue pixel components. When CMS=1, monochrome mode is selected, palette entries are 8 bits wide, 4 or 8 data pins are enabled for single-panel mode, 8 data pins are enabled for dual-panel mode, and the blue dither block is used. 7.6.1.14 LCD Enable (ENB) The LCD enable (ENB) bit enables and quickly disables all LCD controller operations. When ENB=0, the LCD controller is either disabled or in the process of quickly disabling, and all of the LCD pins can be used for GPIO.
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Liquid Crystal Display Controller Table 7-4. LCD Controller Control Register 1 (Sheet 2 of 2) Physical Address 0x4400_0004 Bit LCD Controller Control Register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BLW Reset LCD Controller 0 0 0 0 Bits 0 ELW 0 0 0 0 0 0 0 0 8 7 6 HSW 0 0 0 0 0 Name 0 0 5 4 3 2 1 0 0 0 0 0 PPL 0 0 0 0 0 0 0 0 Description END-OF-LINE PIXEL CLOCK WAIT COUNT (Section 7.6.2.
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Liquid Crystal Display Controller elapsed. When L_LCLK is asserted, the value in HSW is transferred to a 6-bit down counter, which decrements at the programmed pixel clock frequency. When the counter reaches zero, L_LCLK is negated. HSW can be programmed to generate a line clock pulse width ranging from 1 to 64 pixel clock periods. The pixel clock does not toggle during the line clock pulse in passive display mode but does toggle in active display mode.
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Liquid Crystal Display Controller Table 7-5. LCD Controller Control Register 2 Physical Address 0x4400_0008 Bit LCD Controller Control Register 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BFW Reset LCD Controller 0 0 0 0 Bits 0 EFW 0 0 0 0 0 0 0 0 8 7 6 VSW 0 0 0 0 0 Name 0 0 5 4 3 2 1 0 0 0 0 0 LPP 0 0 0 0 0 0 0 0 Description BEGINNING-OF-FRAME LINE CLOCK WAIT COUNT (Section 7.6.3.
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Liquid Crystal Display Controller After the count has elapsed, the VSYNC (L_FCLK) signal is pulsed. EFW generates a wait period ranging from 0 to 255 line clock cycles (EFW=0x00 disables the EOF wait count). L_LCLK does not toggle during the generation of the EFW line clock periods. In passive mode, set EFW to zero so that no EOF wait states are generated. Use VSW exclusively in passive mode to insert line clock wait states.
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Liquid Crystal Display Controller 7.6.3.4 Lines Per Panel (LPP) The lines per panel (LPP) bit field specifies the number of lines or rows present on the LCD panel being controlled. In single-panel mode, it represents the total number of lines for the entire LCD display. LPP is used to count the correct number of line clocks that must occur before the frame clock can be pulsed. In dual-panel mode, it represents half the number of lines of the entire LCD display, which is split into two panels.
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Liquid Crystal Display Controller Table 7-6. LCD Controller Control Register 3 (Sheet 2 of 2) Physical Address 0x4400_000C X 0 0 0 Bits Name 20 VSP 0 VSP X HSP X PCP X BPP OEP reserved Reset LCD Controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 DPC Bit LCD Controller Control Register 3 0 0 0 0 API 0 0 0 8 7 6 5 ACB 0 0 0 0 0 0 4 3 2 1 0 0 0 0 PCD 0 0 0 0 0 0 0 0 Description VERTICAL SYNC POLARITY (Section 7.6.4.
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Liquid Crystal Display Controller 0b100 = 16-bit pixels 0b101–0b111 = reserved 7.6.4.3 Output Enable Polarity (OEP) In active display mode (LCCR0[PAS]=1), the OEP bit selects the active and inactive states of the output enable signal (L_BIAS). In this mode, the AC bias pin serves as an enable that signals the off-chip device when data is actively being driven using the pixel clock, which continuously toggles in active mode. When OEP=0, L_BIAS is active high and inactive low.
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Liquid Crystal Display Controller 7.6.4.7 AC Bias Pin Transitions Per Interrupt (API) The 4-bit API field specifies the number of AC bias pin (L_BIAS) transitions to count before setting the LCSR[ACS] status bit that signals an interrupt request. After the LCD controller is enabled, the value in API is loaded to a 4-bit down counter, and the counter decrements each time L_BIAS is inverted. When the counter reaches zero, it stops, and the LCSR[ABC] count bit is set.
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Liquid Crystal Display Controller • • • • • • Number of panels (single or dual) Display type (monochrome or color) Number of pixel clock wait states programmed at the beginning and end of each line Number of line clocks inserted at the beginning and end of each frame Width of the VSYNC signal in active mode or VSW line clocks inserted in passive mode Width of the frame clock or HSYNC signal. All of these factors alter the time duration from one frame transmission to the next.
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Liquid Crystal Display Controller 7.6.5.1 Frame Descriptors Although the FDADRx registers are loaded by software, the other DMA registers can only be loaded indirectly from DMA frame descriptors.
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Liquid Crystal Display Controller memory location at the beginning of the palette data. The size of the palette data must be four 16bit entries for 1- and 2-bit pixels, sixteen 16-bit entries for 4-bit pixels, or 256 16-bit entries for 8bit pixels. If this is a pixel-data descriptor, FSADRx points to the beginning of the frame buffer in memory. This address is incremented as the DMAC fetches from memory. If desired, the DMA Frame ID Register can hold the initial frame source address.
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Liquid Crystal Display Controller 7.6.5.5 LCD DMA Command Registers (LDCMDx) Registers LDCMD0 and LDCMD1, corresponding to DMA channels 0 and 1, contain configuration fields and the length of the current descriptor for the DMA channel. On reset, the bits in these register are initialized to zero. Reserved bits must be written with zeros and reads from reserved bits must be ignored. Table 7-10 shows the bit layout.
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Liquid Crystal Display Controller Software must load the palette at least once after enabling the LCD. Otherwise, the palette entries will not be initialized, and the frame data will not have a valid frame palette to reference. The palette must not be loaded if the LCD is operating in 16-bit pixel mode. Note: 7.6.5.5.2 Never set the PAL bit in LDCMD1, since the palette is always loaded with Channel 0.
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Liquid Crystal Display Controller Note: In dual-panel mode, write to both FBR0 and FBR1 in order to branch properly. Table 7-11.
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Liquid Crystal Display Controller Table 7-12. LCD Controller Status Register (Sheet 1 of 2) LCD Controller Bits Name 31:11 — X X X X X X X X X X X X X X 0 0 0 0 0 0 1 0 LDD X 2 SOF X 3 BER X 4 IUL X 5 ABC X 6 OU X QD Reset X 7 BS reserved 8 EOF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 SINT Bit LCD Controller Status Register 1 IUU Physical Address 0x4400_0038 0 0 0 0 0 Description Reserved – Write with zeros.
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Liquid Crystal Display Controller Table 7-12.
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Liquid Crystal Display Controller 7.6.7.4 LCD Quick Disable Status (QD) QD is set when LCD enable (LCCR0[ENB]) is cleared and the DMA controller finishes any current data burst. When QD is set, an interrupt request is made to the interrupt controller (if the interrupt controller is unmasked (LCCR0[QDM]=0)). This forces the LCD controller to stop immediately and quit driving the LCD pins. Quick disable is intended for use with sleep shutdown. 7.6.7.
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Liquid Crystal Display Controller 7.6.7.10 Start Of Frame Status (SOF) SOF status is set after the DMA controller has loaded a new descriptor and that descriptor has the start of frame interrupt bit set (LDCMDx[SOFINT]=1). When SOF is set, an interrupt request is made to the interrupt controller if it is unmasked (LCCR0[SFM]=0). In dual-panel mode (LCCR0[SDS]=1), both DMA channels are enabled, and SOF is set only after both channels’ descriptors have been loaded. SOF remains set until cleared by software.
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Liquid Crystal Display Controller (DSTN) displays. The default, recommended setting is 0x00AA5500. This setting provides superior display results in most cases. This is a write-only register. Write reserved bits with zeros and ignore reads from reserved bits. Table 7-14.
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Liquid Crystal Display Controller Table 7-15.
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Liquid Crystal Display Controller 7.6.10.4 TMED Frame Number Adjuster Enable (FNAME) The frame number adjuster enable bit allows the frame number adjuster to add an offset to the current frame number before the value is sent through the algorithm. Setting this bit enables the addition of the current frame number to a value composed from the row and column counters. This value comes from one of the two look up matrices which is selected by TMED[FNAM]. 7.6.10.
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Liquid Crystal Display Controller Table 7-16.
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Synchronous Serial Port Controller 8 This chapter describes the Synchronous Serial Port Controller’s (SSPC) signal definitions and operation for the Intel® PXA26x Processor Family. 8.1 Overview The SSPC is a full-duplex synchronous serial interface and can connect to a variety of external analog-to-digital (A/D) converters, audio and telecom codecs, and other devices that use serial protocols for transferring data.
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Synchronous Serial Port Controller SSPEXTCLK is an external clock (input through GPIO27) that replaces the standard 3.6864-MHz clock used to generate the serial bit-rate clock (SSPSCLK). The external clock is also divided by the value in SSCR0[SCR]. If SSP operation is disabled, the five SSP pins are available for GPIO use. See Chapter 4, “System Integration Unit” for details on configuring pin direction and interrupt capabilities. 8.
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Synchronous Serial Port Controller • SSPRXD – Receive signal for inbound data, from peripheral to system. A data frame can be configured to contain from 4 to 16 bits. Serial data is transmitted most significant bit first. The SSPC supports three formats: Motorola SPI, Texas Instruments SSP, and National Microwire. The three formats have significant differences, as described below.
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Synchronous Serial Port Controller . Figure 8-1. Texas Instruments’ Synchronous Serial Frame* Format SSPSCLK ... SSPSFRM ... SSPTXD Bit Bit ... Bit<1> Bit<0> SSPRXD Bit Bit ... Bit<1> Bit<0> MSB 4 to 16 Bits LSB Single Transfer SSPSCLK ... ... ... ... SSPSFRM SSPTX /RX Bit<0> Bit Bit ... Bit<1> Bit<0> Bit Bit ... Bit<1> Bit<0> Continuous Transfers 8.4.1.2 SPI Format Details The SPI format has four sub-modes.
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Synchronous Serial Port Controller Figure 8-2 shows one of the four configurations for the Motorola SPI frame format for single and back-to-back frame transmissions. Figure 8-2. Motorola SPI* Frame Format SSPSCLK ... SSPSFRM ... SSPTXD Bit SSPRXD Bit Bit ... Bit<1> Bit<0> Bit ... Bit<1> Bit<0> MSB 4 to 16 Bits LSB Single Transfer SSPSCLK ... ... ... ... SSPSFRM SSPTX /RX Bit<0> Bit Bit ... Bit<1> Bit<0> Bit Bit ...
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Synchronous Serial Port Controller Figure 8-3 shows the National Microwire frame format with 8-bit command words for single and back-to-back frame transmissions. Figure 8-3. National Microwire* Frame Format SSPSCLK ... ... ... ... SSPSFRM SSPTXD Bit<7> ... Bit<0> 8-Bit Control SSPRXD ... 1 Clk ... Bit ... Bit<0> 4 to 16 Bits Single Transfer SSPSCLK ... ... ... ... ... ... SSPSFRM SSPTXD Bit<0> ... Bit<7> ... Bit<0> 1 Clk SSPRXD ... 1 Clk Bit ... Bit<0> ... Bit ..
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Synchronous Serial Port Controller 8.5.1 Using Programmed I/O Data Transfers Data words are 32 bits wide, but only 16-bit samples are transferred. Only the lower 2 bytes of a 32-bit word have valid data. The upper 2 bytes are not used and include invalid data that must be discarded. The processor can fill or empty FIFOs in response to an interrupt from the FIFO logic. Each FIFO has a programmable interrupt threshold.
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Synchronous Serial Port Controller “fullness” threshold that triggers an interrupt. Write to these registers before the SSP is enabled after reset and only change when SSP is disabled. • The SSPC Data Register (SSDR) is mapped as one 32-bit location that consists of two 16-bit registers. One register is for write operations and transfers data to the transmit FIFO. The other is for read operations and takes data from the receive FIFO.
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Synchronous Serial Port Controller Table 8-2.
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Synchronous Serial Port Controller The transmit logic in the SSPC left-justifies the data sample according to the DSS bits before the sample is transmitted. Data sizes of 1, 2, and 3 bits are reserved and produce unpredictable results in the SSPC. In National Microwire frame format, this bit field selects the size of the received data and the transmitted data is 8 or 16 bits long. 8.7.1.
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Synchronous Serial Port Controller 8.7.1.5 Serial Clock Rate (SCR) Use the 8-bit serial clock rate (SCR) bit-field to select the SSPC bit rate. The SSPC has 256-bit rates, from 7.2 Kbps to 1.8432 Mbps. The serial clock generator uses the internal 3.6864-MHz clock or an external clock provided through SSPEXTCLK. The clock is divided by 2, then divided by the programmable SCR value (0 to 255) plus 1 to generate the serial clock (SSPSCLK).
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Synchronous Serial Port Controller Table 8-3. SSP Control Register 1 (SSCR1) Bitmap and Definitions (Sheet 2 of 2) Bits Name 9:6 TFT 13:10 RFT 31:14 — 0 0 3 2 1 0 RIE 0x0 4 TIE 0x0 5 SPO X 6 LBM Reset 7 SPH Reserved 8 TFT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RFT Bit SSP Control Register 1 (SSCR1) MWDS 0x4100 0004 0 0 0 0 Description TRANSMIT FIFO THRESHOLD: Sets threshold level at which transmit FIFO generates an interrupt or DMA request.
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Synchronous Serial Port Controller Note: 8.7.2.4 Loop back mode cannot be used with Microwire frame format. Serial Clock Polarity (SPO) The serial clock polarity bit (SPO) selects the SSPSCLK signal’s inactive state in the Motorola SPI format (FRF=00). For SPO=0, the SSPSCLK is held low in the inactive or idle state when the SSP is not transmitting/receiving data. When SPO=1, the SSPSCLK is held high during the inactive/ idle state.
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Synchronous Serial Port Controller Figure 8-4. Motorola SPI* Frame Formats for SPO and SPH Programming SSPSCLK SPO=0 ... SSPSCLK SPO=1 ... SSPSFRM ... SSPTXD Bit SSPRXD Bit MSB Bit ... Bit<1> Bit<0> Bit ... Bit<1> Bit<0> 4 to 16 Bits LSB SPH = 0 SSPSCLK SPO=0 ... SSPSCLK SPO=1 ... SSPSFRM ... SSPTXD SSPRXD Bit Bit MSB Bit ... Bit<1> Bit<0> Bit ... Bit<1> Bit<0> 4 to 16 Bits LSB SPH = 1 8.7.2.
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Synchronous Serial Port Controller 8.7.2.8 Receive FIFO Interrupt/DMA Threshold (RFT) This 4-bit value sets the level at or above which the FIFO controller triggers a DMA service interrupt and, if enabled, an interrupt request. Refer to Table 8-4 for suggested RFT values associated with DMA servicing. Be careful not to set the RFT value too high for your system or the FIFO could overrun because of the bus latencies caused by other internal and external peripherals.
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Synchronous Serial Port Controller Note: Both FIFOs are cleared when the SSPC is reset or a zero is written to the SSCR0[SSE] bit. Table 8-5. SSP Data Register (SSDR) Bitmap and Definitions 0x4100 0010 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reset Bits 15:0 31:16 8.7.
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Synchronous Serial Port Controller Table 8-6.
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Synchronous Serial Port Controller 8.7.4.2 Receive FIFO Not Empty Flag (RNE) (read-only, non-interruptible) The Receive FIFO Not Empty Flag (RNE) is a read-only bit that is set when the receive FIFO contains one or more entries and is cleared when the FIFO is empty. Because CPU interrupt requests are only made when the receive FIFO threshold has been met or exceeded, the RNE bit can be polled when programmed I/O removes remaining bytes of data from the receive FIFO. This bit does not request an interrupt.
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Synchronous Serial Port Controller 8.7.4.7 Transmit FIFO Level The 4-bit Transmit FIFO Level bit indicates the number of entries currently in the transmit FIFO. 8.7.4.8 Receive FIFO Level The 4-bit receive FIFO Level bit indicates the one less than number of entries in the receive FIFO. 8.7.5 SSP Register Address Map Table 8-7 shows the SSP registers associated with the SSP and their physical addresses. Table 8-7.
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Synchronous Serial Port Controller 8-20 Intel® PXA26x Processor Family Developer’s Manual
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Inter-Integrated Circuit Bus Interface Unit 9 This chapter describes the Inter-Integrated Circuit (I2C) bus interface unit, including the operation modes and setup for the Intel® PXA26x Processor Family. 9.1 Overview The I2C bus was created by the Phillips Corporation and is a serial bus with a two-pin interface. The SDA data pin is used for input and output functions and the SCL clock pin is used to control and reference the I2C bus.
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Inter-Integrated Circuit Bus Interface Unit Table 9-2. I2C Bus Definitions I2C Device Definition Transmitter Sends data to the I2C bus. Receiver Receives data from the I2C bus. Master Initiates a transfer, generates the clock signal, and terminates the transactions. Slave Device addressed by a master. Multi-master More than one master can attempt to control the bus at the same time without corrupting the message.
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Inter-Integrated Circuit Bus Interface Unit 9.3.1 Operational Blocks The I2C unit is connected to the peripheral bus. The processor interrupt mechanism can be used to notify the CPU that there is activity on the I2C bus. Polling can be used instead of interrupts. The I2C unit consists of the two wire interface to the I2C bus, an 8-bit buffer for passing data to and from the processor, a set of control and status registers, and a shift register for parallel/serial conversions.
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Inter-Integrated Circuit Bus Interface Unit While the I2C unit is idle, it defaults to slave-receive mode. This allows the interface to monitor the bus and receive any slave addresses intended for the processor. When the I2C unit receives an address that matches the 7-bit address found in the I2C Slave Address Register (ISAR) or the general call address (see Section 9.4.7, “General Call Address”), the interface either remains in slave-receive mode or transitions to slave-transmit mode.
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Inter-Integrated Circuit Bus Interface Unit Table 9-4. START and STOP Bit Definitions STOP bit STAR T bit 0 0 Condition No START or STOP Notes I2C unit sends a no START or STOP condition. Used when multiple data bytes need to be transferred. I2C unit sends a START condition and transmit the 8-bit IDBR’s contents. The IDBR must contain the 7-bit address and the R/nW bit before a START is initiated.
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Inter-Integrated Circuit Bus Interface Unit 9.3.3.2 No START or STOP Condition Use the no START or STOP condition (ICR[START]=0, ICR[STOP]=0) in master-transmit mode while the I2C unit is transmitting multiple data bytes (see Figure 9-2). Software writes the data byte and the I2C unit sets the ISR[ITE] bit and clears the ICR[TB] bit. The software then writes a new byte to the IDBR and sets the ICR[TB] bit, which initiates the new byte transmission.
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Inter-Integrated Circuit Bus Interface Unit 8. Repeated START (Repeat Step 1) or STOP 9.4.1 Serial Clock Line (SCL) Generation When the I2C unit is in master-transmit or master-receive mode, it generates the I2C clock output. The SCL clock is generated by setting the ICR[FM] bit for either 100 KBit/sec or 400 Kbit/sec operation. 9.4.2 Data and Addressing Management The I2C Data Buffer Register (IDBR) and the I2C Slave Address Register (ISAR) manage data and slave addressing. The IDBR (see Section 9.9.
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Inter-Integrated Circuit Bus Interface Unit Figure 9-4. Data Format of First Byte in Master Transaction Read/Write Transaction (0) Write (1) Read 7-Bit I2C Slave Address 7 MSB 0 LSB The first byte transmission must be followed by an ACK pulse from the addressed slave. When the transaction is a write, the I2C unit remains in master-transmit mode and the addressed slave device stays in slave-receive mode.
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Inter-Integrated Circuit Bus Interface Unit In master-transmit mode, if the target slave-receiver device cannot generate the acknowledge pulse, the SDA line remains high. The lack of an acknowledge NAK causes the I2C unit to set the ISR[BED] bit and generate the associated interrupt when enabled. The I2C unit automatically generates a STOP condition and aborts the transaction. In master-receive mode, the I2C unit sends a negative acknowledge (NAK) to signal the slavetransmitter to stop sending data.
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Inter-Integrated Circuit Bus Interface Unit Figure 9-6. Clock Synchronization During the Arbitration Procedure The first master to complete its high period pulls the SCL line low. Wait State Start Counting High Period CLK1 CLK2 SCL The master with the longest clock period holds the SCL line low. 9.4.4.2 SDA Arbitration Arbitration on the SDA line can continue for a long time because it starts with the address and R/ nW bits and continues through the data bits.
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Inter-Integrated Circuit Bus Interface Unit If the I2C unit loses arbitration as the address bits are transferred and it is not addressed by the address bits, the I2C unit resends the address when the I2C bus becomes free. A resend is possible because the IDBR and ICR registers are not overwritten when arbitration is lost.
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Inter-Integrated Circuit Bus Interface Unit Table 9-5. Master Transactions (Sheet 1 of 2) I2C Master Action Mode of Operation Generate clock output Master-transmit Write target slave address to IDBR Master-receive Master-transmit Master-receive Definition Master drives the SCL line. ICR[SCLE] bit must be set. ICR[IUE] bit must be set. CPU writes to IDBR bits 7-1 before a START condition enabled. First seven bits sent on bus after START. See Section 9.3.3, “Start and Stop Bus States”.
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Inter-Integrated Circuit Bus Interface Unit Table 9-5. Master Transactions (Sheet 2 of 2) I2C Master Action Mode of Operation Definition I2C master operation data receive mode. Eight bits are read from the serial bus, collected in the shift register then transferred to the IDBR after the ICR[ACKNAK] bit is read. The CPU reads the IDBR when the ISR[IRF] bit is set and the ICR[TB] bit is clear. If IDBR Receive Full Interrupt is enabled, it is signalled to the CPU.
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Inter-Integrated Circuit Bus Interface Unit . Figure 9-8. Master-Receiver Read from Slave-Transmitter START Slave Address R/nW 1 First Byte Read Data Byte ACK Data Byte ACK ACK STOP N Bytes + ACK Slave to Master Master to Slave Default Slave-Receive Mode \ Figure 9-9.
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Inter-Integrated Circuit Bus Interface Unit 9.4.6 Slave Operations Table 9-6 describes how the I 2C unit operates as a slave device. Table 9-6. Slave Transactions I2C Slave Action Mode of Operation Definition I2C unit monitors all slave address transactions. ICR[IUE] bit must be set. Slave-receive (default mode) Slave-receive only I2C unit monitors bus for START conditions.
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Inter-Integrated Circuit Bus Interface Unit Figure 9-11 through Figure 9-13 are examples of I2C transactions and show the relationships between master and slave devices. Figure 9-11. Master-Transmitter Write to Slave-Receiver START Slave Address First Byte Master to Slave R/nW 0 Data Byte ACK Write ACK Data Byte ACK STOP NAK STOP N Bytes + ACK Slave to Master Figure 9-12.
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Inter-Integrated Circuit Bus Interface Unit master-transmitter. Figure 9-14 shows a general call address transaction. The least significant bit of the second byte, called B, defines the transaction. Table 9-7 shows the valid values and definitions when B=0. The I2C unit supports sending and receiving general call address transfers on the I2C bus. When software sends a general call message from the I2C unit, it must set the ICR[GCD] bit to prevent the I2C unit from responding as a slave.
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Inter-Integrated Circuit Bus Interface Unit 9.5 Slave Mode Programming Examples The following sub-sections describe slave mode programming. 9.5.1 Initialize Unit To initialize the unit: 1. Set the slave address in the ISAR. 2. Enable desired interrupts in the ICR. 3. Set the ICR[IUE] bit to enable the I2C unit. 9.5.2 Write n Bytes as a Slave To write n bytes as a slave: 1. When a Slave Address Detected interrupt occurs. Read ISR: slave address detected (1), unit busy (1), R/nW bit (1), ACK/NAK (0) 2.
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Inter-Integrated Circuit Bus Interface Unit 9.5.3 Read n Bytes as a Slave To read n bytes as a slave: 1. When a slave address detected interrupt occurs. Read ISR: slave address detected (1), unit busy (1), R/nW bit (0) 2. Write a 1 to the ISR[SAD] bit to clear the interrupt. 3. Return from interrupt. 4. Set ICR[TB] bit to initiate the transfer. 5. When an IDBR receive full interrupt occurs. Read ISR: IDBR receive full (1), ACK/NAK (0), R/nW bit (0) 6. Read IDBR to get the received byte. 7.
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Inter-Integrated Circuit Bus Interface Unit 5. Write a 1 to the ISR[ALD] bit if set. If the master loses arbitration, it performs an address retry when the bus becomes free. The arbitration loss detected interrupt is disabled to allow the address retry. 6. Load data byte to be transferred in the IDBR. 7. Initiate the write. Clear ICR[START], set ICR[STOP], set ICR[ALDIE], set ICR[TB] 8. When an IDBR transmit empty interrupt occurs (unit is sending STOP).
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Inter-Integrated Circuit Bus Interface Unit 7. When an IDBR transmit empty interrupt occurs. Read ISR: IDBR transmit empty (1), unit busy (1), R/nW bit (0) 8. Write a 1 to the ISR[ITE] bit to clear interrupt. 9. Repeat steps 5-8 one time. 10. Load target slave address and R/nW bit in the IDBR. R/nW must be 1 for a read. 11. Send repeated start as a master. Set ICR[START], clear ICR[STOP], clear ICR[ALDIE], set ICR[TB] 12. When an IDBR transmit empty interrupt occurs.
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Inter-Integrated Circuit Bus Interface Unit 13. Read IDBR data. 14. Initiate STOP abort condition (STOP with no data transfer). Set ICR[MA] Note: 9.7 If a NAK is not sent in step 11, the next transaction must involve another data byte read. Glitch Suppression Logic The I2C unit has built-in glitch suppression logic that suppresses glitches of 60ns or less. This is within the 50ns glitch suppression specification. 9.
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Inter-Integrated Circuit Bus Interface Unit Table 9-9. I2C Bus Monitor Register - IBMR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Reset 0 0 0 0 0 0 0 31:2 — 1 SCLS 0 SDAS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 SDAS I2C Reserved Bit I2C Bus Monitor Register SCLS Physical Address 4030_1680 1 1 Reserved SCL STATUS: This bit continuously reflects the value of the SCL pin.
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Inter-Integrated Circuit Bus Interface Unit Table 9-10. I2C Data Buffer Register - IDBR (Sheet 2 of 2) Physical Address 4030_1688 I2C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 3 2 1 0 0 0 0 0 IDB Reserved Bit I2C Data Buffer Register 0 0 0 0 0 0 0 0 0 0 0 2 7:0 I C DATA BUFFER: IDB Buffer for I2C bus send/receive data. I2C Control Register- ICR 9.9.
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Inter-Integrated Circuit Bus Interface Unit Table 9-11. I2C Control Register - ICR (Sheet 2 of 3) Physical Address 4030_1690 0 0 0 0 0 0 0 0 0 START 0 1 STOP 0 2 TB 0 3 ACKNAK 0 4 MA 0 5 SCLE 0 6 IUE 0 7 GCD 0 8 ITEIE 0 BEIE 0 IRFIE 0 SSDIE 0 ALDIE 0 SADIE 0 UR 0 FM Reset I2 C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved Bit I2C Control Register 0 0 0 0 0 0 0 0 BUS ERROR INTERRUPT ENABLE: 0 – Disable interrupt.
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Inter-Integrated Circuit Bus Interface Unit Table 9-11. I2C Control Register - ICR (Sheet 3 of 3) Physical Address 4030_1690 0 0 0 0 0 0 0 0 0 START 0 1 STOP 0 2 TB 0 3 ACKNAK 0 4 MA 0 5 SCLE 0 6 IUE 0 7 GCD 0 8 ITEIE 0 BEIE 0 IRFIE 0 SSDIE 0 ALDIE 0 SADIE 0 UR 0 FM Reset I2C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved Bit I2C Control Register 0 0 0 0 0 0 0 0 TRANSFER BYTE: Used to send/receive a byte on the I2C bus.
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Inter-Integrated Circuit Bus Interface Unit Table 9-12. I2C Status Register - ISR (Sheet 1 of 2) Physical Address 4030_1698 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UB 0 0 ACKNAK 0 — 1 IBB 0 2 SSD 0 3 ALD 0 4 ITE 0 5 IRF 0 31:11 6 GCAD 0 7 SAD Reset 8 BED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RWM I2 C Reserved Bit I2C Status Register 0 0 0 0 0 0 0 0 0 0 Reserved BUS ERROR DETECTED: 0 – No error detected.
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Inter-Integrated Circuit Bus Interface Unit Table 9-12. I2C Status Register - ISR (Sheet 2 of 2) Physical Address 4030_1698 0 0 0 0 0 0 0 0 0 0 0 0 0 RWM 0 0 UB 0 1 ACKNAK 0 2 0 0 0 0 ALD 0 3 SSD 0 4 ITE 0 5 IRF 0 6 GCAD 0 7 SAD Reset 8 BED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 IBB I2C Reserved Bit I2C Status Register 0 0 0 0 0 0 0 UNIT BUSY: 2 0 – I2C unit not busy. UB 1 – Set when the I2C unit is busy.
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Universal Asynchronous Receiver/ Transmitter 10 This chapter describes the three universal asynchronous receiver/transmitter (UART) serial ports without hardware flow control. Because the Hardware UART is configured differently than the other three, it is described in Section 17, “Hardware UART”. The serial ports are controlled via direct memory access (DMA) or programmed I/O. This section describes the full function UART, Bluetooth UART, and standard UART. These UARTS use the same programming model. 10.
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Universal Asynchronous Receiver/Transmitter 10.2 Overview Each serial port contains a UART and a slow infrared transmit encoder and receive decoder that conforms to the IrDA Serial Infrared (SIR) Physical Layer Link Specification. Each UART performs serial-to-parallel conversion on data characters received from a peripheral device or a modem and parallel-to-serial conversion on data characters received from the processor. The processor can read a UART’s complete status during functional operation.
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Universal Asynchronous Receiver/Transmitter 10.3 Signal Descriptions Table 10-1 lists and describes each external signal that is connected to a UART module. The pins are connected through the system integration unit to GPIOs. Refer to Section 4.1, “GeneralPurpose Input/Output” for details on the GPIOs. Table 10-1. UART Signal Descriptions (Sheet 1 of 2) Name Type Description RXD Input SERIAL INPUT – Serial data input to the receive shift register.
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Universal Asynchronous Receiver/Transmitter Table 10-1. UART Signal Descriptions (Sheet 2 of 2) Name Type nRI Description RING INDICATOR – When low, indicates that the modem or data set has received a telephone ringing signal. The nRI signal is a Modem Status input whose condition can be tested by reading Bit 6 (RI) of the MSR. Bit 6 is the complement of the nRI signal.
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Universal Asynchronous Receiver/Transmitter Each UART has two FIFOs: one transmit and one receive. The transmit FIFO is 64 bytes deep and eight bits wide. The receive FIFO is 64 bytes deep and 11-bits wide. Three bits are used for tracking errors. The UART can use NRZ coding to represent individual bit values. NRZ coding is enabled when the Interrupt Enable Register’s (IER) bit 5, IER[5] is set to high. A one is represented by a line transition and a zero is represented by no line transition.
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Universal Asynchronous Receiver/Transmitter . Table 10-2. UART Register Addresses as Offsets of a Base 10.4.2.
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Universal Asynchronous Receiver/Transmitter 10.4.2.2 Transmit Holding Register (THR) In non-FIFO mode, the THR holds the data byte that is to be transmitted next. When the TSR is emptied, the contents of the THR are loaded in the TSR and the LSR[TDRQ] is set to a 1. In FIFO mode, a write to the THR puts data into the top of the FIFO. The data at the front of the FIFO is loaded to the TSR when that register is empty. Table 10-4.
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Universal Asynchronous Receiver/Transmitter Table 10-5.
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Universal Asynchronous Receiver/Transmitter Note: When DMA requests are enabled and an interrupt occurs, software must first read the LSR to see if an error interrupt exists, then check the IIR for the source of the interrupt. When the last error byte is read from the FIFO, DMA requests are automatically enabled. Software is not required to check for the error interrupt if DMA requests are disabled because an error interrupt only occurs when DMA requests are enabled.
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Universal Asynchronous Receiver/Transmitter Table 10-7.
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Universal Asynchronous Receiver/Transmitter Table 10-8. Interrupt Conditions Priority Level Interrupt origin 1 (highest) Receiver Line Status – One or more error bits were set 2 Received Data is available – In FIFO mode, trigger level was reached. In non-FIFO mode, RBR has data. 2 Character Timeout Indication occurred – Occurs only in FIFO mode, when data is in the receive FIFO but no data has been sent for a set time period.
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Universal Asynchronous Receiver/Transmitter Table 10-10. Interrupt Identification Register Decode Interrupt ID Bits 3 2 1 0 Priority 0 0 0 1 — 0 1 1 0 Highest 0 1 0 0 10.4.2.
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Universal Asynchronous Receiver/Transmitter Table 10-11.
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Universal Asynchronous Receiver/Transmitter 10.4.2.7 Line Control Register (LCR) The LCR specifies the format for the asynchronous data communications exchange. The serial data format consists of a start bit, five to eight data bits, an optional parity bit, and one, one and a half, or two stop bits. The LCR has bits that allow access to the divisor latch and bits that can cause a break condition. Table 10-12.
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Universal Asynchronous Receiver/Transmitter Table 10-12.
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Universal Asynchronous Receiver/Transmitter Table 10-13. Line Status Register – LSR (Sheet 1 of 2) UART 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 1 0 DR 0 3 OE 0 4 PE 0 5 BI Reset 6 FE 7 TEMT 8 TDRQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved Bit Line Status Register FIFOE Base+0x14 0 0 0 0 0 Read only Bits Name 31:8 — Description Reserved FIFO ERROR STATUS: 7 FIFOE In non-FIFO mode, this bit is 0.
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Universal Asynchronous Receiver/Transmitter Table 10-13.
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Universal Asynchronous Receiver/Transmitter Table 10-14.
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Universal Asynchronous Receiver/Transmitter Table 10-14. Modem Control Register – MCR (Sheet 2 of 2) 8 7 6 5 4 OUT1 RTS DTR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OUT2 UART 0 0 0 0 0 0 0 0 0 Reserved Bit Modem Control Register LOOP Base+0x10 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 2 1 0 Read/Write Bits Name Description TEST BIT: 2 OUT1 This bit is used only in Loopback mode. It is ignored otherwise.
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Universal Asynchronous Receiver/Transmitter Note: When bit 0, 1, 2, or 3 is set, a modem status interrupt is generated if IER[MIE] is set. Table 10-15.
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Universal Asynchronous Receiver/Transmitter 10.4.2.11 Scratchpad Register (SPR) The read/write SPR has no effect on the UART. It is intended as a scratchpad register for use by the programmer. It is included for 16550 compatibility. Table 10-16.
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Universal Asynchronous Receiver/Transmitter After the processor reads one character from the receive FIFO or a new start bit is received, the character timeout indication interrupt is cleared and the timeout is reset. If a character timeout indication interrupt has not occurred, the timeout is reset when a new character is received or the processor reads the receive FIFO. 10.4.3.3 Transmit Interrupt Transmit interrupts can only occur when the transmit FIFO and transmit interrupt are enabled.
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Universal Asynchronous Receiver/Transmitter Note: 10.4.5.1 Ensure that the DMAC has finished previous receive DMA requests before the error interrupt handler begins to clear the errors from the FIFO. Trailing Bytes in the Receive FIFO Trailing bytes occur when the number of entries in the receive FIFO is less than its trigger level and no more data is being received. In such a case, a receive DMA request is not generated. To read the trailing bytes follow these steps: 1.
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Universal Asynchronous Receiver/Transmitter Table 10-17.
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Universal Asynchronous Receiver/Transmitter Figure 10-3. IR Transmit and Receive Example START UART TRANSMIT SHIFT VALUE BIT 1 0 0 0 1 1 0 0 STOP BIT IR ENCODER OUTPUT (TXD PIN VALUE) RXD PIN VALUE IR DECODER OUTPUT START BIT UART RECEIVE 1 0 0 0 1 0 1 0 SHIFT VALUE STOP BIT The top line in Figure 10-3 shows an asynchronous transmission as it is sent from the UART. The second line shows the pulses generated by the IR encoder at the TXD pin.
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Universal Asynchronous Receiver/Transmitter Note: The SIR TXD output pin is automatically held deasserted when the RCVEIR bit is set. Before setting the RCVEIR bit, check that the TEMT bit is 1. While receiving, any data placed in the transmit FIFO will not be held. Only add data to the transmit FIFO while not receiving. To start transmission, the RCVEIR bit must be cleared. To disable SIR, disable the IrDA LED first, if possible.
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Universal Asynchronous Receiver/Transmitter Table 10-19.
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Universal Asynchronous Receiver/Transmitter 10-28 Intel® PXA26x Processor Family Developer’s Manual
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Fast Infrared Communication Port 11 The Fast Infrared Communications Port (FICP) for the Intel® PXA26x Processor Family operates at half-duplex and provides direct connection to commercially available Infrared Data Association (IrDA) compliant LED transceivers. The FICP is based on the 4-Mbps IrDA standard and uses four-position pulse modulation (4PPM) and a specialized serial packet protocol developed for IrDA transmission.
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Fast Infrared Communication Port 11.2.1 Four-Position Pulse Modulation Four-position pulse modulation (4PPM) is used to transmit data at the high-speed rate, 4.0 Mbps. Data bits are encoded two at a time by placing a single 125 ns light pulse in one of four timeslots. The four timeslots are collectively termed a chip. Bytes are encoded one at a time. They are divided into four individual 2-bit pairings called nibbles. The least significant nibble is transmitted first.
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Fast Infrared Communication Port Figure 11-2. 4PPM Modulation Example Original Byte Order Reordered Nibbles Nibble 3 1 0 Nibble 2 1 1 Nibble 1 0 0 Nibble 0 0 1 0 1 Nibble 0 0 0 Nibble 1 1 1 Nibble 2 1 0 Nibble 3 1 2 3 4 Chips Timeslots 1 2 3 4 1 2 3 4 1 2 3 4 1 125 ns 2 3 4 4PPM Data 48 MHz Receive data sample counter frequency = 6/pulse width. Each timeslot is sampled on the third cloc 11.2.
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Fast Infrared Communication Port 11.2.3 Address Field A transmitter uses the 8-bit address field to target a receiver when multiple stations are connected to the same set of serial lines. The address allows up to 255 stations to be uniquely addressed (0x00 to 0xFE). The broadcast address 0xFF is used to send messages to all of the connected stations. For reception, FICP control register 1 (ICCR1) is used to program a unique receive address.
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Fast Infrared Communication Port 11.2.7 Baud Rate Generation The baud rate is derived by dividing a fixed 48-MHz clock by six. Using a digital PLL, the 8-MHz baud (or timeslot) clock for the receive logic is synchronized with the 4PPM data stream each time a transition is detected on the receive data line. To encode a 4-Mbps data stream, the required chip frequency is 2.0 MHz, with four timeslots per chip at a frequency of 8.0 MHz.
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Fast Infrared Communication Port If the data field contains any invalid chips (such as 0011, 1010, 1110) the frame aborts and the oldest byte in the temporary FIFO is moved to the receive FIFO, the remaining temporary FIFO entries are discarded, the end-of-frame (EOF) tag is set in the FIFO entry that holds the last valid byte of data, and the receiver logic searches for the preamble. The receive logic continuously searches for the 8-chip stop flag.
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Fast Infrared Communication Port At the end of each transmitted frame, the FICP sends a pulse called the serial infrared interaction pulse (SIP). A SIP must be sent at least every 500 ms to ensure that low-speed devices (115.2 Kbps and slower) do not interfere with devices that transmit at higher speeds. The SIP simulates a start bit that causes low-speed devices to stay off the air for at least another 500 ms. The SIP pulse forces the transmit data pin high for 1.625 µs and low for 7.
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Fast Infrared Communication Port The core must also read bytes from the FIFO until ICSR0[EIF] is cleared if there are errors in FIFO entries below the DMA trigger level. When the entries below the DMA trigger level no longer contain status flags, DMA requests are enabled. 11.3 Fast Infrared Communications Port Register Descriptions The FICP has six registers: three control registers, one data register, and two status registers.
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Fast Infrared Communication Port Table 11-2.
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Fast Infrared Communication Port Table 11-2.
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Fast Infrared Communication Port Table 11-3.
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Fast Infrared Communication Port Table 11-4. Fast Infrared Communication Port Control Register 2 (Sheet 2 of 2) Fast Infrared Communication Port Control Register 2 (ICCR2) 7 6 5 4 3 Reset 0 0 0 Bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name 0 0 0 0 0 2 0 0 0 0 0 1 1 1 0 TRIG 8 TXP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved Bit FICP RXP 0x4080 0008 0 0 Description RECEIVE PIN POLARITY SELECT.
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Fast Infrared Communication Port each entry is removed, the EIF bit must be checked to determine if any set end or error tag remains and the procedure is repeated until all set tags are flushed from the FIFO’s bottom entries. When EIF is cleared, DMA service for the receive FIFO is re-enabled. Both FIFOs are cleared when the processor is reset. The transmit FIFO is cleared when TXE is 0. The receive FIFO is cleared when RXE is 0. Table 11-5.
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Fast Infrared Communication Port . Table 11-6.
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Fast Infrared Communication Port . Table 11-7.
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Fast Infrared Communication Port 11.4 Fast Infrared Communications Port Register Locations Table 11-8 shows the registers associated with the FICP block and the physical addresses used to access them. Table 11-8.
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Universal Serial Bus Device Controller 12 This section describes the Universal Serial Bus (USB) protocol and its implementation-specific options for device controllers for the Intel® PXA26x Processor Family. These options include endpoint number, type, and function; interrupts to the Intel® XScale™ Microarchitecture (core); and a transmit/receive FIFO interface. A working knowledge of the USB standard is vital to using this section effectively.
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Universal Serial Bus Device Controller service request is generated when a packet has been received. The DMA engine services the UDC FIFOs in 32-byte increments. Interrupts are also generated when the FIFO encounters a short packet or zero-length packet. Endpoint 0 has a 16-entry long, 8-bit wide FIFO that can only be read or written by the processor. For endpoints 1-15, the UDC uses its dual-ported memory to hold data for a Bulk OUT transaction while the transaction is checked for errors.
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Universal Serial Bus Device Controller Data flow is relative to the USB host. IN packets represent data flow from the UDC to the host. OUT packets represent data flow from the host to the UDC. The FIFOs for the bulk and isochronous endpoints are double-buffered so one packet can be processed as the next is assembled. While the UDC transmits an IN packet from a particular endpoint, the core can load the same endpoint for the next frame transmission.
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Universal Serial Bus Device Controller host detects a disconnect when an SE0 persists for more than 2.5 µs (30 bit times). When the UDC is connected to the USB cable, the pull-up resistor on the UDC+ pin causes D+ to be pulled above the single-ended high threshold level. After 2.5 µs, the host detects a connect. After the host detects a connect, the bus is in the Idle state because UDC+ is high and UDC- is low.
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Universal Serial Bus Device Controller The PID is 1 byte wide and always follows the sync field. The first four bits contain an encoded value that represents packet type (token, data, handshake, and special), packet format, and type of error detection. The last four bits contain a check field that ensures the PID is transmitted without errors. The check field is generated by performing a ones complement of the PID.
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Universal Serial Bus Device Controller Table 12-3. IN, OUT, and SETUP Token Packet Format 12.3.4.2 8 bits 8 bits 7 bits 4 bits 5 bits Sync PID Address Endpoint CRC5 Start of Frame Packet Type An SOF is a special type of token packet that the host issues at a nominal interval of once every 1 ms +/- 0.0005 ms. SOF packets consist of a sync, a PID, a frame number (incremented after each frame is transmitted), and a CRC5 field (see Table 12-4).
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Universal Serial Bus Device Controller 12.3.5 Transaction Formats Packets are assembled into groups to form transactions. The USB protocol uses four different transaction formats. Each transaction format is specific to a particular type of endpoint: bulk, control, interrupt, or isochronous. Endpoint 0, by default, is a control endpoint and receives only control transactions.
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Universal Serial Bus Device Controller 12.3.5.3 Control Transaction Type The host uses control transactions to configure endpoints and query their status. Like bulk transactions, control transactions begin with a setup packet, followed by an optional data packet, then a handshake packet. Control transactions, by default, use DATA0 type transfers. Table 12-9 shows the four types of control transactions. Table 12-9.
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Universal Serial Bus Device Controller • • • • • • • Data transfer direction: host to device, device to host Data transfer type: standard, class, vendor Data recipient: device, interface, endpoint, other Number of bytes to transfer Index or offset Value: used to pass a variable-sized data parameter Device request Table 12-11 shows a summary of all device requests. Refer to the Universal Serial Bus Specification Revision 1.1 for a full description of host device requests. Table 12-11.
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Universal Serial Bus Device Controller 12.3.7 Configuration In response to the GET_DESCRIPTOR command, the user device sends back a description of the UDC configuration. The UDC can physically support more data channel bandwidth than the USB specification allows. When the device responds to the host, it must specify a legal USB configuration.
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Universal Serial Bus Device Controller Figure 12-2. Self-Powered Device USB 5V 5 V to 3.3 V GPIOn 470K GPIOx 1.5K USB D+ UDC D+ 0 ohm (optional) USB D- UDC D0 ohm (optional) USB GND Board GND 12.4.1.1 When GPIOn and GPIOx are Different Pins The GPIOn and GPIOx pins can be any GPIO pins. GPIOn must be a GPIO that can wake the device from sleep mode. After a reset, GPIOx is configured as an input. This causes the UDC+ line to float.
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Universal Serial Bus Device Controller 12.4.2 Bus-Powered Devices The processor does not support bus-powered devices because it is required to consume less that 500 µA when the host issues a suspend (see Section 7.2.3 of the USB Specification, version 1.1). The processor cannot limit the amount of current it consumes to 500 µA unless it enters sleep mode. When the processor enters sleep mode it resets the USB registers and does not respond to its host-assigned address. 12.
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Universal Serial Bus Device Controller 14. When the host executes the STATUS OUT stage (zero-length OUT), the UDC sets the UDDCS0[OPR] bit, which causes an interrupt. 15. Software enters the ISR routine and determines that the UDCCS0[OPR] bit is set, the UDCCS0[SA] bit is clear, and its internal state machine is EP0_END_XFER. Software clears the UDCCS0[OPR] bit and transfers its internal state machine to EP0_IDLE. 16. Software clears the UDC interrupt bit and returns from the interrupt service routine.
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Universal Serial Bus Device Controller 16. Software clears the UDC interrupt bit and returns from the interrupt service routine. If the host sends another SETUP command during these steps, the software must terminate the first SETUP command and start the new command. 12.5.3 Case 3: EP0 Control Write With or Without a Premature Status Stage 1. When software starts, it initializes a software state machine to EP0_IDLE.
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Universal Serial Bus Device Controller the wrong amount of data was sent, software cleans up any buffer pointers and disregards the received data. 20. Software changes its internal state machine to EP0_IDLE. 21. Software clears the UDC interrupt bit and returns from the interrupt service routine. If the host sends another SETUP command during these steps, the software must terminate the first SETUP command and start the new command. 12.5.4 Case 4: EP0 No Data Command 1.
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Universal Serial Bus Device Controller 1. During the SETUP VENDOR command, software enables the DMA engine and masks the EP1 interrupt. The DMA start address must be aligned on a 16-byte boundary. a. If the packet size is 64 bytes, software transfers the all the data in one DMA descriptor and sets the UDCCS1[TSP] bit in the second DMA descriptor. b.
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Universal Serial Bus Device Controller 2. The host PC sends a BULK-OUT. 3. The DMA engine reads data from the EP2 data FIFO (UDDR2). 4. Steps 2 and 3 repeat until all the data has been read from the host. 5. If the software receives an EP2 interrupt it completes this process: a. If UDCCS2[RNE] is clear and UDCCS2[RSP] is set, the data packet was a zero-length packet. b.
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Universal Serial Bus Device Controller 1. During the SETUP VENDOR command, software enables the DMA engine and masks the EP3 interrupt. The DMA start address must be aligned on a 16-byte boundary. a. If the packet size is 256 bytes, software transfers the all the data in one DMA descriptor. b. If the packet size is less than 256 bytes, software sets up a string of descriptors in which the odd numbered descriptors point to the data and the even numbered descriptors are writes to the UDCCS1[TSP] bit. 2.
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Universal Serial Bus Device Controller When software receives a SETUP VENDOR command to set up an EP4 ISOCHRONOUS OUT transaction, it may take one of three courses of action, as appropriate for the chosen operating model: • Configure the DMA engine and disable the EP4 interrupt to allow the DMA engine to handle the transaction. • Enable the EP4 interrupt to allow the core to directly handle the transaction. • Enable the SOF interrupt to handle the transaction on a frame count basis. 12.5.8.
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Universal Serial Bus Device Controller 6. Return from interrupt. 7. Steps 2 through 6 repeat until all the data has been read from the host. 12.5.8.3 Software Enables the SOF Interrupt If software enables the SOF interrupt to handle the transaction on a frame count basis: 1. Software disables the UDCCS4 Interrupt by setting UICR0[IM4] to a 1 and enables the SOF interrupt in the UFNHR register by setting UFNHR[SIM] to a 0. 2.
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Universal Serial Bus Device Controller b. If UDCCR[UDA] is a 1, there is currently no USB reset on the bus and software enables future reset interrupts by clearing the UDCCR[REM] bit. 3. Return from interrupt. 4. The host either asserts a USB reset or negates a USB reset. 5. The UDC generates a reset interrupt. 6. Software determines that the UDCCR[RSTIR] bit is set and clears the interrupt by writing a 1 to the UDCCR[RSTIR] bit.
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Universal Serial Bus Device Controller address for the 16 x 8 data FIFO that can be used to transmit and receive data. Endpoint 0 also has a write count register that is used to determine the number of bytes the USB host controller has sent to endpoint 0. 12.6.1 UDC Control Register The UDC control register (UDCCR) contains seven control bits: one to enable the UDC, one to show activity, and five to show status and associated control functions. 12.6.1.
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Universal Serial Bus Device Controller 12.6.1.7 Reset Interrupt Request (RSTIR) The reset interrupt request register is set when the host issues a reset. When the host issues a reset, the entire UDC is reset. The RSTIR bit retains its state so software can determine that the design was reset. If REM is zero, RSTIR being set does not generate an interrupt but status continues to be updated. 12.6.1.
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Universal Serial Bus Device Controller Table 12-12. UDC Control Register (Sheet 2 of 2) 0h 4060 0000 Bit Rese t UDCCR Read/Write and Read-Only 31:8 7 6 5 4 3 2 1 0 Reserved REM RSTIR SRM SUSIR RESIR RSM UDA UDE X 1 0 1 0 0 0 0 0 Bits Name 2 RSM Description DEVICE RESUME (read/write 1 to set): 0 – Maintain UDC suspend state 1 – Force UDC out of suspend UDC ACTIVE (read-only): 1 UDA 0 – UDC currently receiving a USB reset. 1 – UDC currently not receiving a USB reset.
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Universal Serial Bus Device Controller 12.6.2.3 Flush Tx FIFO (FTF) The flush Tx FIFO bit triggers the reset of the endpoint 0 transmit FIFO. It is set when software writing a one or when the UDC receives an OUT packet from the host on endpoint 0. This bit always reads back a zero value. 12.6.2.4 Device Remote Wake Up Feature (DRWF) The host indicates the state of the device-remote-wake-up feature by sending a Set Feature command or a Clear Function command.
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Universal Serial Bus Device Controller Table 12-13. UDC Endpoint 0 Control Status Register 0h 4060 0010 Bit Rese t UDCCS0 Read/Write 31:8 7 6 5 4 3 2 1 0 Reserved SA RNE FST SST DRWF FTF IPR OPR X 0 0 0 0 0 0 0 0 Bits Name 0 OPR 1 IPR 2 FTF 3 DRWF Description OUT PACKET READY (read/write 1 to clear): 1 – OUT packet ready. IN PACKET READY (always read 0/write 1 to set): 1 – IN packet ready.
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Universal Serial Bus Device Controller 12.6.3.2 Transmit Packet Complete (TPC) The transmit packet complete bit is set by the UDC when an entire packet is sent to the host. When this bit is set, the IRx bit in the appropriate UDC status/interrupt register is set if transmit interrupts are enabled. This bit can be used to validate the other status/error bits in the endpoint(x) control/ status register. The UDCCSx[TPC] bit is cleared by writing a 1 to it.
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Universal Serial Bus Device Controller 12.6.3.8 Transmit Short Packet (TSP) The software uses the transmit short packet bit to indicate that the last byte of a data transfer to the FIFO has occurred. This indicates to the UDC that a short packet or zero-sized packet is ready to transmit. Software must not set this bit if a 64-byte packet is to be transmitted. When the data packet is successful transmitted, the UDC clears this bit. Table 12-14.
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Universal Serial Bus Device Controller 12.6.4.1 Receive FIFO Service (RFS) The receive FIFO service bit is set if the receive FIFO has one complete data packet in it and the packet has been error checked by the UDC. A complete packet may be 64 bytes, a short packet, or a zero packet. This bit is not cleared until all data has been read from both buffers. 12.6.4.2 Receive Packet Complete (RPC) The receive packet complete bit is set by the UDC when an OUT packet is received.
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Universal Serial Bus Device Controller 12.6.4.7 Receive FIFO Not Empty (RNE) The receive FIFO not empty bit indicates that unread data remains in the receive FIFO. This bit must be polled when the UDCCSx[RPC] bit is set to determine if there is any data in the FIFO that the DMA did not read. The receive FIFO must continue to be read until this bit clears or data will be lost. 12.6.4.
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Universal Serial Bus Device Controller Table 12-15. UDC Endpoint x Control Status Register, Where x is 2, 7, or 12 (Sheet 2 of 2) Bit Rese t 0h 4060 0018 UDCCS2 Read/Write 0h 4060 002C UDCCS7 Read/Write 0h 4060 0040 UDCCS12 Read/Write 31:8 7 6 5 4 3 2 1 0 Reserved RSP RNE FST SST DME Reserved RPC RFS X 0 0 0 0 0 0 0 0 Bits Name 6 RNE Description RECEIVE FIFO NOT EMPTY (read-only): 0 – Receive FIFO empty. 1 – Receive FIFO not empty. 12.6.
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Universal Serial Bus Device Controller 12.6.5.3 Flush Tx FIFO (FTF) The Flush Tx FIFO bit triggers a reset for the endpoint's transmit FIFO. The Flush Tx FIFO bit is set when software writes a 1 to it or when the host performs a SET_CONFIGURATION or SET_INTERFACE. The bit’s read value is zero. 12.6.5.4 Transmit Underrun (TUR) The transmit underrun bit is be set if the transmit FIFO experiences an underrun. When the UDC experiences an underrun, UDCCSx[TUR] generates an interrupt.
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Universal Serial Bus Device Controller Table 12-16.
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Universal Serial Bus Device Controller 12.6.6.2 Receive Packet Complete (RPC) The receive packet complete bit gets set by the UDC when an OUT packet is received. When this bit is set, the IRx bit in the appropriate UDC status/interrupt register is set if receive interrupts are enabled. This bit can be used to validate the other status/error bits in the endpoint(x) control/status register. The UDCCSx[RPC] bit is cleared by writing a 1 to it. 12.6.6.
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Universal Serial Bus Device Controller Table 12-17. UDC Endpoint x Control Status Register, Where x is 4, 9, or 14 Bit Rese t 0h 4060 0020 UDCCS4 Read/Write 0h 4060 0034 UDCCS9 Read/Write 0h 4060 0048 UDCCS14 Read/Write 31:8 7 6 5 4 3 2 1 0 Reserved RSP RNE Reserved Reserved DME ROF RPC RFS X 0 0 0 0 0 0 0 0 Bits Name 0 RFS Description RECEIVE FIFO SERVICE (read-only): 0 – Receive FIFO has less than 1 data packet. 1 – Receive FIFO has 1 or more data packets.
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Universal Serial Bus Device Controller 12.6.7.2 Transmit Packet Complete (TPC) The transmit packet complete bit is be set by the UDC when an entire packet is sent to the host. When this bit is set, the IRx bit in the appropriate UDC status/interrupt register is set if transmit interrupts are enabled. This bit can be used to validate the other status/error bits in the endpoint(x) control/status register. The UDCCSx[TPC] bit is cleared by writing a 1 to it.
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Universal Serial Bus Device Controller 12.6.7.8 Transmit Short Packet (TSP) Software uses the transmit short to indicate that the last byte of a data transfer has been sent to the FIFO. This indicates to the UDC that a short packet or zero-sized packet is ready to transmit. Software must not set this bit if a packet of 8 bytes is to be transmitted. When the data packet is successfully transmitted, the UDC clears this bit. Table 12-18.
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Universal Serial Bus Device Controller 12.6.8.1 Interrupt Mask Endpoint x (IMx), Where x is 0 through 7 The UICR0[IMx] bit is used to mask or enable the corresponding endpoint interrupt request, USIR0[IRx]. When the mask bit is set, the interrupt is masked and the corresponding bit in the USIR0 register is not allowed to be set. When the mask bit is cleared and an interruptible condition occurs in the endpoint, the appropriate interrupt bit is set.
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Universal Serial Bus Device Controller 12.6.9.1 Interrupt Mask Endpoint x (IMx), where x is 8 through 15. The UICR1[IMx] bit is used to mask or enable the corresponding endpoint interrupt request, USIR1[IRx]. When the mask bit is set, the interrupt is masked and the corresponding bit in the USIR1 register is not allowed to be set. When the mask bit is cleared and an interruptible condition occurs in the endpoint, the appropriate interrupt bit is set.
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Universal Serial Bus Device Controller 12.6.10 UDC Status/Interrupt Register 0 (USIR0) The UDC status/interrupt registers (USIR0 and USIR1) contain bits that generate the UDC’s interrupt request. Each bit in the UDC status/interrupt registers is logically ORed together to produce one interrupt request. When the ISR for the UDC is executed, it must read the UDC status/ interrupt register to determine why the interrupt occurred. USIRx is level sensitive.
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Universal Serial Bus Device Controller 12.6.10.7 Endpoint 6 Interrupt Request (IR6) The interrupt request bit gets set if the IM6 bit in the UDC interrupt control register is cleared and the IN packet complete (TPC) in UDC endpoint 6 control/status register gets set. The IR6 bit is cleared by writing a one to it. 12.6.10.
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Universal Serial Bus Device Controller 12.6.11.2 Endpoint 9 Interrupt Request (IR9) The interrupt request bit is set if the IM9 bit in the UDC interrupt control register is cleared and the OUT packet ready (RPC) or receiver overflow (ROF) in the UDC endpoint 9 control/status register or the Isochronous Error Endpoint 9 (IPE9) in the UFNHR are set. The IR9 bit is cleared by writing a 1 to it. 12.6.11.
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Universal Serial Bus Device Controller Table 12-22. UDC Status / Interrupt Register 1 0h 4060 005C Bit Rese t 12.6.12 USIR1 Read/Write and Read-Only 31:8 7 6 5 4 3 2 1 0 Reserved IR15 IR14 IR13 IR12 IR11 IR10 IR9 IR8 X 0 0 0 0 0 0 0 0 Bits Name 0 IR8 1 IR9 2 IR10 3 IR11 4 IR12 5 IR13 6 IR14 7 IR15 31:8 — Description INTERRUPT REQUEST ENDPOINT 8 (read/write 1 to clear): 1 – Endpoint 8 needs service.
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Universal Serial Bus Device Controller 12.6.12.3 Isochronous Packet Error Endpoint 9 (IPE9) The isochronous packet error for Endpoint 9 is set if Endpoint 9 is loaded with a data packet that is corrupted. This status bit is used in the interrupt generation of endpoint 9. To maintain synchronization, software must monitor this bit when it services the SOF interrupt and reads the frame number. This bit is not set if the token packet is corrupted or if the sync or PID fields of the data packet are corrupted.
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Universal Serial Bus Device Controller Table 12-23. UDC Frame Number High Register (Sheet 2 of 2) 0h 4060 0060 Bit UFNHR Read 31:8 7 6 5 4 3 Reserved SIR SIM IPE14 IPE9 IPE4 X 0 1 0 0 0 Bits Name 6 SIM Rese t 2 1 0 3-Bit Frame Number MSB 0 0 0 Description SOF INTERRUPT MASK: 0 – SOF interrupt enabled. 1 – SOF interrupt disabled. 12.6.13 7 SIR 31:8 — SOF INTERRUPT REQUEST (read/write 1 to clear): 1 – SOF has been received.
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Universal Serial Bus Device Controller Table 12-25. UDC Byte Count Register x, Where x is 2, 4, 7, 9, 12, or 14 Bit 31:8 0h 4060 0068 UBCR2 Read-Only 0h 4060 006C UBCR4 Read-Only 0h 4060 0070 UBCR7 Read-Only 0h 4060 0074 UBCR9 Read-Only 0h 4060 0078 UBCR12 Read-Only 0h 4060 007C UBCR14 Read-Only 7 6 5 4 Reserved Reset 12.6.
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Universal Serial Bus Device Controller Table 12-26. UDC Endpoint 0 Data Register 0h 4060 0080 Bit 31:8 7 6 Reserved UDDR0 5 4 Read/Write 3 2 1 0 Bottom of Endpoint 0 FIFO (for Reads) X 0 0 0 0 0 0 0 0 31:8 7 6 5 4 3 2 1 0 0 0 Reset Reserved Reset Top of Endpoint 0 FIFO (for Writes) X 0 0 Bits Name 7:0 DATA 0 0 0 0 Description Top/bottom of endpoint 0 FIFO data Read – Bottom of endpoint 0 FIFO data. Write – Top of endpoint 0 FIFO data. 31:8 12.6.
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Universal Serial Bus Device Controller 12.6.17 UDC Data Register x (UDDRx), Where x is 2, 7, or 12 Endpoint(x) is a double-buffered bulk OUT endpoint that is 64 bytes deep. The UDC generates either an interrupt or DMA request as soon as the EOP is received. Since it is double buffered, up to two packets of data may be ready. Via DMA or by direct read from the core, the data can be removed from the UDC.
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Universal Serial Bus Device Controller 12.6.19 UDC Data Register x (UDDRx), Where x is 4, 9, or 14 Endpoint(x) is a double-buffered isochronous OUT endpoint that is 256 bytes deep. The UDC generates an interrupt or DMA request when the EOP is received. Because it is double-buffered, up to two packets of data may be ready. The data can be removed from the UDC via DMA or by a direct read from the core.
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Universal Serial Bus Device Controller 12.6.21 UDC Register Locations Table 12-32 shows the registers associated with the UDC and the physical addresses used to access them. Table 12-32.
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Universal Serial Bus Device Controller Table 12-32.
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Universal Serial Bus Device Controller 12-52 Intel® PXA26x Processor Family Developer’s Manual
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AC97 Controller Unit 13.1 13 Overview The AC97 Controller Unit (ACUNIT) of the Intel® PXA26x Processor Family supports the AC97 revision 2.0 features listed in Section 13.2, “Feature List”. The ACUNIT also supports audio controller link (AC-link). AC-link is a serial interface for transferring digital audio, modem, Micin, codec register control, and status information. The AC97 codec sends the digitized audio samples that the ACUNIT stores in memory.
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AC97 Controller Unit 13.3 Signal Description The AC97 signals form the AC-link, which is a point-to-point synchronous serial interconnect that supports full-duplex data transfers. All digital audio streams, modem line codec streams, and command/status information are communicated over the AC-link. The AC-link uses general purpose I/Os (GPIOs). Software must reconfigure the GPIOs to use them as the AC-link. The AClink pins are listed and described in Table 13-1. Table 13-1.
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AC97 Controller Unit Figure 13-1. Data Transfer Through the AC-link AC97 Controller Unit (ACUNIT) AC-link AC97 Primary Codec nACRESET SDATA_OUT SYNC (48 KHz) SDATA_IN_0 SDATA_IN_1 BITCLK (12.288 MHz) AC97 Secondary Codec 13.4 AC-link Digital Serial Interface Protocol Each AC97 codec incorporates a five-pin digital serial interface that links it to the ACUNIT. AC-link is a full-duplex, fixed-clock, PCM digital stream.
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AC97 Controller Unit Table 13-2. Supported Data Stream Formats (Sheet 2 of 2) Channel Slots Comments Dedicated Microphone Input One input slot Dedicated microphone input stream in support of stereo AEC and other voice applications. I/O Control One output slot One slot dedicated to GPOs on the modem codec. One input slot One slot dedicated to status from GPIs in the modem codec. Data is returned on every frame.
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AC97 Controller Unit Figure 13-3. AC-link Audio Output Frame Tag Phase Data Phase 20.8uS (48 KHz) 12.288 MHz SYNC 81.4 nS BIT_CLK Valid Frame SDATA_OUT End of previous Audio Frame slot(1) slot(2) slot(12) "0" 19 codec ID codec ID Time Slot "Valid" Bits ("1" = time slot contains valid PCM data) 0 Slot 1 19 0 Slot 2 19 0 Slot 3 19 0 Slot 12 A new audio output frame begins with a low-to-high SYNC transition synchronous to BITCLK’s rising edge.
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AC97 Controller Unit Note: 13.4.1.1 When the ACUNIT transmits mono audio sample streams, software must ensure that the left and right sample stream time slots are filled with identical data. Slot 0: Tag Phase In slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) that flags the validity for the entire audio frame. If the valid frame bit is a 1, the current audio frame contains at least one slot time of valid data.
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AC97 Controller Unit 3. Write a non-zero value (0b01, 0b10, 0b11) to the codec ID field (slot 0, bits 1 and 0) 4. Specify the read/write direction of the access (slot 1, bit 19). 5. Specify the index to the codec register (slot 1, bits 18-12) 6. If the access is a write, write the data to the command data port (slot 2, bits 19-4). Table 13-3.
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AC97 Controller Unit 13.4.1.6 Slot 5: Modem Line Codec Audio output frame slot 5 contains the MSB justified modem DAC input data if the line codec is supported. The optional modem DAC input resolution can be implemented as 16, 18, or 20 bits. If the modem line codec is supported, the ACUNIT driver determines the DAC resolution at boot time. During normal runtime operation, the ACUNIT fills all trailing non-valid bit positions in the slot with zeroes.
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AC97 Controller Unit Figure 13-5. AC97 Input Frame Tag Phase Data Phase 20.8uS (48 KHz) 12.288 MHz SYNC 81.4 nS BIT_CLK Codec Ready SDATA_IN End of previous Audio Frame slot(1) slot(2) slot(12) "0" "0" "0" Time Slot "Valid" Bits ("1" = time slot contains valid PCM data) 19 0 19 Slot 1 0 Slot 2 19 0 Slot 3 19 0 Slot 12 A new audio input frame begins when SYNC transitions from low to high. The low to high transition is synchronous to BITCLK’s rising edge.
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AC97 Controller Unit 13.4.2.2 Slot 1: Status Address Port/SLOTREQ bits The status port monitors the status for the ACUNIT functions including, but not limited to, mixer settings and power management. Audio input frame slot 1’s stream echoes the control register index for the data to be returned in slot 2, if the controller tags slots 1 and 2 valid during slot 0.
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AC97 Controller Unit Note: 13.4.2.3 Slot requests for slots 3 and 4 are always set or cleared in tandem (both set or both cleared). Slot 2: Status Data Port The status data port delivers 16-bit control register read data. Table 13-6. Input Slot 2 Bit Definitions Note: 13.4.2.4 Bit Name Description Bit(19:4) Control register read data Filled with zeroes if AC97 tags it invalid Bit(3:0) Reserved Filled with zeroes If slot 2 is tagged invalid, the ACUNIT fills the entire slot with zeroes.
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AC97 Controller Unit 13.4.2.9 Slot 12: I/O Status The GPIOs configured as inputs return their status on this slot every frame. The data returned on the latest frame is accessible to software through the codec register at address 0x54 in the modem codec I/O space. Only the 16 MSBs are used to return GPIO status. Bit 0 in the LSBs indicates a GPI Input Interrupt event. See the AC97 revision 2.0 spec for more information. Reads from codec address 0x54 are not transmitted across the link.
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AC97 Controller Unit 13.5.2 Waking up the AC-link 13.5.2.1 Wake up triggered by the Codec To wake up the AC-link a codec drives its SDATA_IN to a logic high level. The rising edge triggers the resume interrupt if that codec’s resume enable bit is set to a 1. The CPU then wakes up the codec using the cold or warm reset sequence. The ACUNIT uses a warm reset to wake up the primary codec. The codec detects a warm reset when SYNC is driven high for a minimum of 1 µs and the BITCLK is absent.
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AC97 Controller Unit 13.5.2.2.1 Cold AC97 Reset A cold reset is generated when the nACRESET pin is asserted through the GCR[COLD_RST]. Asserting and de-asserting nACRESET activates BITCLK (supplied by the codec) and SDATA_OUT. All AC97 control registers are initialized to their default power on reset values. nACRESET is an asynchronous AC97 input. 13.5.2.2.2 Warm AC97 Reset A warm AC97 reset reactivates the AC-link without altering the current AC97 register values.
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AC97 Controller Unit Note: After it is enabled, the ACUNIT requests the DMA immediately to fill the transmit FIFO. Note: The ACUNIT registers do not store the status of the DMA requests or information regarding the number of data samples in each FIFO. As a result, programmed I/O must not be used in place of DMA requests for data transfers. Only the DMA can access the FIFOs. Accesses are made through the data registers. The DMA controller accesses FIFO data in 8-, 16-, or 32-byte blocks.
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AC97 Controller Unit does not set the codec-ready bit, GCR[PCRDY] for the primary codec or GCR[SCRDY] for the secondary codec. 13.6.2 Trailing bytes If the transmit buffers do not have 32-byte resolution, the trailing bytes in the transmit FIFO are not transmitted. A transmit buffer must be padded with zeroes if it is smaller than a multiple of 32 bytes. Regardless of burst size, the DMA descriptor length must be a multiple of 32 bytes to prevent audio artifacts from being introduced on the interface.
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AC97 Controller Unit transmit valid data in certain frames. For example, if the controller sends out 480 frames, and the codec instructs the controller not to send valid data in 39 of those 480 frames, the codec would have in effect sampled data at 44.1 KHz. When the codec transmits data (controller-receive mode), it can use the same algorithm to transmit valid frames with some empty ones mixed in between. All data transfers across the AC-link are synchronized to SYNC’s rising edge.
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AC97 Controller Unit 13.8.1.2 Receive FIFO Errors Channel-specific status bits are updated during receive overrun conditions and trigger interrupts when enabled. Refer to Table 13-13, “PCM_In Status Register”, Table 13-17, “Mic-In Status Register”, and Table 13-22, “Modem-In Status Register” for details regarding the status bits. During receive over-run conditions, data that the codec sends is not recorded. 13.8.
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AC97 Controller Unit • Audio codec registers • Modem codec registers Channel specific data registers are for FIFO accesses and the PCM, modem, and mic-in FIFOs each have a register. A write access to one of these registers updates the written data in the corresponding transmit FIFO. A read access to one of these registers flushes out an entry from the corresponding receive FIFO. Note: Register tables show organization and individual bit definitions.
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AC97 Controller Unit Table 13-7. Register Mapping Summary (Sheet 2 of 2) Address Name 0x4050_0118 MISR 0x4050_011C through 0x4050_013C Modem In Status Register — 0x4050_0140 Reserved MODR 0x4050_0144 through 0x4050_01FC (0x4050_0200 through 0x4050_02FC) with all in increments of 0x00004 (0x4050_0300 through 0x4050_03FC) with all in increments of 0x00004 (0x4050_0400 through 0x4050_04FC) with all in increments of 0x0000_0004 (0x4050_0500 through 0x4050_05FC) with all in increments of 0x00004 13.
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AC97 Controller Unit Table 13-8.
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AC97 Controller Unit 13.8.3.3 Global Status Register (GSR) Table 13-9.
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AC97 Controller Unit Table 13-9.
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AC97 Controller Unit 13.8.3.4 PCM-Out Control Register (POCR) Table 13-10.
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AC97 Controller Unit 13.8.3.6 PCM-Out Status Register (POSR) Table 13-12.
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AC97 Controller Unit 13.8.3.8 Codec Access Register (CAR) Table 13-14.
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AC97 Controller Unit Figure 13-9. PCM Transmit and Receive Operation Transmit Data Processor/DMA Write Receive Data Processor/DMA Read RxEntry15 TxEntry15 PCDR Register PCM Transmit FIFO 31 TxEntry3 RxEntry3 RxFIFO Read TxFIFO Written TxEntry2 PCM Receive FIFO 0 RxEntry2 RxEntry1 TxEntry1 Right 31 13.8.3.10 TxEntry0 Left 16 15 Right 31 0 RxEntry0 Left 16 15 0 Mic-In Control Register (MCCR) Table 13-16.
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AC97 Controller Unit 13.8.3.11 Mic-In Status Register (MCSR) Table 13-17. Mic-In Status Register AC97 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 0 0 0 0 Reserved Reset 0 0 0 0 0 0 0 0 Bits Name 31:5 — 0 0 0 0 0 0 0 4 3 2 0 0 FIFOE Bit MCSR Register 0 0 0 0 0 0 0 0 0 1 0 0 0 Reserved Physical Address 4050_0018 Description Reserved FIFO ERROR (FIFOE): 0 – No receive FIFO error has occurred.
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AC97 Controller Unit Figure 13-10. Mic-in Receive-Only Operation Receive Data Processor/DMA Read RxEntry15 MCDR Register 0x0000 Mic-in Receive FIFO 31 0 16 15 RxFIFO Read RxEntry3 RxEntry2 RxEntry1 RxEntry0 15 13.8.3.13 0 Modem-Out Control Register (MOCR) Table 13-19.
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AC97 Controller Unit 13.8.3.14 Modem-In Control Register (MICR) Table 13-20.
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AC97 Controller Unit 13.8.3.16 Modem-In Status Register (MISR) Table 13-22. Modem-In Status Register AC97 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 0 0 0 0 Reserved Reset 0 0 0 0 0 0 0 0 Bits Name 31:5 — 0 0 0 0 0 0 0 4 3 2 0 0 FIFOE Bit MISR Register 0 0 0 0 0 0 0 0 0 1 0 0 0 Reserved Physical Address 4050_0118 Description Reserved FIFO ERROR (FIFOE): 0 – No receive FIFO error has occurred.
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AC97 Controller Unit Figure 13-11. Modem Transmit and Receive Operation Transmit data Processor/DMA Write RxEntry15 TxEntry15 0x0000 Modem Transmit FIFO 15 13.8.3.18 Receive Data Processor DMA Read 31 MODR Register 1615 Modem Receive FIFO 0 TxEntry3 RxEntry3 TxEntry2 RxEntry2 TxEntry1 RxEntry1 TxEntry0 RxEntry0 15 0 0 Accessing Codec Registers Each codec has up to sixty-four 16-bit registers that are addressable internal to the codec at halfword boundaries (16-bit boundaries).
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AC97 Controller Unit Table 13-24.
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AC97 Controller Unit Table 13-24.
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Inter-Integrated Circuit Sound Controller 14 Inter-Integrated Circuit Sound (I2S) is a protocol for digital stereo audio. The I2S controller (I2SC) functional block for the Intel® PXA26x Processor Family controls the I2S link (I2SLINK), which is a low-power four-pin serial interface for stereo audio. The I2S interface, the Audio CODEC ‘97 (AC’97) interface, and the ASSP may not be used at the same time. 14.
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Inter-Integrated Circuit Sound Controller 14.2 Signal Descriptions SYSCLK is the clock on which all other clocks in the I2S unit are based. SYSCLK generates a frequency between approximately 2 MHz and 12.2 MHz by dividing down the PLL clock with a programmable divisor. This frequency is always 256 times the audio sampling frequency. SYSCLK is driven out of the processor system only if BITCLK is configured as an output.
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Inter-Integrated Circuit Sound Controller To configure SYNC and SDATA_OUT as outputs, follow these steps: 1. Program SYSUNIT’s GPIO Direction Register (GPDR). See Section 4.1.3.2, “GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)” on page 4-9 for details regarding the GPDR. 2. Program SYSUNIT’s GPIO Alternate Function Select Register (GAFR). See Section 4.1.3.6, “GPIO Alternate Function Register (GAFR)” on page 4-17 for details regarding the GAFR. To configure SDATA_IN as an input, follow these steps: 1.
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Inter-Integrated Circuit Sound Controller 3. Optional: Programmed I/O may be used for priming the transmit FIFO with a few samples (ranging from 1 to 16). If the I2SLINK is enabled with an empty transmit FIFO, a Transmit Under-run error bit will be set in the Status register. For further details, see Section 14.6.3, “Serial Audio Controller I2S/MSB-Justified Status Register (SASR0)”. This is hence an optional step, which prevents such an error.
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Inter-Integrated Circuit Sound Controller Asserting the DREC bit in SACR1 has the following effects: 1. I2SLINK recording activity is disabled. The frame or data sample, in the midst of which the recording is disabled, could have invalid data (some data bits will be over-written with zeros). To avoid this, disable record only after the transfer of valid data. 2. Receive FIFO pointers are reset to zero. 3. Receive FIFO fill-level is reset to zero. 4.
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Inter-Integrated Circuit Sound Controller The BITCLK, as shown in Table 14-2, is different for different sampling frequencies. If the BITCLK is chosen as an output, the Audio Clock Divider Register divides the 147.46-MHz PLL clock to generate the SYSCLK. The SYSCLK is further divided by four to generate the BITCLK. The sampling frequency is the frequency of the SYNC signal, which is generated by dividing the BITCLK by 64. See Section 14.6.
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Inter-Integrated Circuit Sound Controller Figure 14-1 and Figure 14-2 provide timing diagrams that show formats for I2S and MSB-justified modes of operations. Data is transmitted and received in frames of 64 BITCLK cycles. Each frame consists of a Left sample and a Right sample. Each sample holds 16-bit of valid data. The LSB 16-bit of each sample is padded with zeros. In the Normal I2S mode, the SYNC is low for the Left sample and high for the Right sample.
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Inter-Integrated Circuit Sound Controller • The Status Register signals the state of the FIFO buffers and the status of the interface that is selected by the common control register. • The Interrupt Registers include the Interrupt Mask Register, the Interrupt Clear Register, and the Interrupt Test Register. 14.6.1 Serial Audio Controller Global Control Register (SACR0) This register controls common I2S functions. All bits are read/write. Table 14-3 shows the bit layout of SACR0.
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Inter-Integrated Circuit Sound Controller Table 14-3.
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Inter-Integrated Circuit Sound Controller Table 14-4. FIFO Write/Read table EFWR STRF Description Normal CPU/DMA write/read condition: • A write access to the Data Register writes a transmit FIFO entry. 0 x • A read access to the Data Register reads out a receive FIFO entry. • I2SLINK reads from the transmit FIFO and writes to the receive FIFO. CPU or DMA only writes and reads transmit FIFO: • A write access to the Data Register writes a transmit FIFO entry.
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Inter-Integrated Circuit Sound Controller Table 14-6.
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Inter-Integrated Circuit Sound Controller Table 14-7.
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Inter-Integrated Circuit Sound Controller 14.6.4 Serial Audio Clock Divider Register (SADIV) This register is used for generating six different BITCLK frequencies and hence six different sampling frequencies. All bits are read/write. Table 14-8 shows the bit layout of SADIV. The reset value, 0x0000001A, defaults to a sampling frequency of 22.05 KHz.
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Inter-Integrated Circuit Sound Controller Table 14-9. SAICR Bit Descriptions Serial Audio Interrupt Clear Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Bit 8 7 6 5 TUR I2S Controller ROR Physical Address 0x4040-0018 r r Reserved Reset r r r r r Bits r r r r r r r r r r r r r r Name r r r r r r 3 2 1 0 Reserved r r r r r Description 31:7 — 6 ROR Clear receive FIFO overrun interrupt and ROR status bit in SASR0.
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Inter-Integrated Circuit Sound Controller Table 14-11. SADR Bit Descriptions Physical Address 0x4040-0080 Bit I2S Controller Serial Audio Data Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 DTH Reset 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 DTL 0 0 0 0 Bits Name 31:16 DTH Right data sample 15:0 DTL Left data sample 0 0 0 0 0 0 0 0 0 0 0 0 Description Figure 14-3.
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Inter-Integrated Circuit Sound Controller Table 14-12.
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15 MultiMediaCard Controller 15.1 Overview The Intel® PXA26x Processor Family MultiMediaCard (MMC) controller acts as a link between the software used to access the processor and the MMC stack (a set of memory cards). The MMC controller is designed to support the MMC system, a low-cost data storage and communications system. A detailed description of the MMC system is available through the MMC Association’s web site at www.mmca.org.
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MultiMediaCard Controller The MMC bus connects the card stack to the controller. The software and controller can turn the MMC clock on and off. The card stack and the controller communicate serially through the command and data lines and implement a message-based protocol. The messages consist of the following tokens: • Command: a 6-byte command token starts an operation. The command set includes card initialization, card register reads and writes, data transfers, etc.
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MultiMediaCard Controller . Figure 15-2. MMC Mode Operation Without Data Token from host to card(s) from host to card Command MMCMD from card to host Command Response MMDAT Operation (No Response) Operation (No Data) Figure 15-3. MMC Mode Operation With Data Token from host to MMCMD Command from stop command stops data transfer data to/from Command Response Response Data Stream MMDAT Data Transfer Operation Data Stop Operation In SPI mode, not all commands are available.
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MultiMediaCard Controller Figure 15-5. SPI Mode Read Operation from card to from host to MMCMD data from card to Next Command Command MMDAT Response Data Block CRC Figure 15-6. SPI Mode Write Operation from host to MMCMD MMDAT Note: from card to Command data from host to Data response new Command Data Block Response Data Response Busy One- and three-byte data transfers are not supported with this controller. Data transfers of 10 or more bytes are supported for stream writes only.
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MultiMediaCard Controller Table 15-4. MMC Signal Description Signal Name Input/Output Description MMCLK Output Clock signal to MMC MMCMD BiDirectional Command line MMDAT BiDirectional Data line MMCCS0 Output Chip Select 0 (used only in SPI mode) MMCCS1 Output Chip Select 1 (used only in SPI mode) The MMCLK, MMCCS0, and MMCCS1 signals are routed through alternate functions within the GPIO. Refer to Section 4.
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MultiMediaCard Controller address in the argument portion of the command token that is protected with a 7-bit CRC (see Table 15-1). For a description of the identification process when multiple cards are connected to a system, refer to the Card Identification Process as described in the MultiMediaCard System Specification, Version 2.1. There are five formats for the response token, including a no response token. The response token length is 48 or 136 bits and may be protected with a 7-bit CRC.
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MultiMediaCard Controller The command token is protected with a 7-bit CRC. The card always sends a response to a command token. The response token has four formats, including an 8-bit error response. The length of the response tokens is one, two, or five bytes. SPI mode offers a non protected mode. In this mode, CRC bits of the command, response, and data tokens are still required in the tokens but these bits are ignored by the card and the controller.
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MultiMediaCard Controller 3. Restart the clock. Software must not stop the clock when it attempts to read the receive FIFOs or write the transmit FIFOs. When the clock stops, it resets the pointers in the FIFOs and any data left in the FIFOs can not be transmitted or accessed. When the receive FIFOs are empty and the MMC_STAT[DATA_TRAN_DONE] is set, software may stop the clock. The software can specify the clock divisor of the 20-Mhz clock by setting the MMC_CLKRT register.
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MultiMediaCard Controller 15.2.8.2 Receive Data FIFO, MMC_RXFIFO The two receive data FIFOs are read only by the software and are readable on a single byte basis. They are dual FIFOs, where each FIFO is 32 entries of 1-byte data. Access to the FIFOs is controlled by the controller and depends on the status of the FIFOs. Both FIFOs and their controls are cleared to a starting state after a system reset and at the beginning of all command sequences. The FIFOs swap between the software and MMC bus.
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MultiMediaCard Controller 15.2.8.3 Transmit Data FIFO, MMC_TXFIFO The two transmit data FIFOs are written only by the software and are writable on a single byte basis. They are dual FIFOs, where each FIFO is 32 entries of one byte data. Access to the FIFOs is controlled by the controller and depends on the status of the FIFOs. Both FIFOs and their controls are cleared to a starting state after a system reset and at the beginning of all command sequences. The FIFOs swap between the software and MMC bus.
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MultiMediaCard Controller For the DMA, use three descriptors of 32 bytes and 32-byte bursts and one descriptor of two more bytes and 8-, 16- or 32-byte bursts and program the descriptor to set an interrupt, for the software to write the MMC_PRTBUF[BUF_PART_FULL] bit. • Transmit 105 bytes: Write 32 bytes three times, then write nine more bytes.
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MultiMediaCard Controller — MMC_CLKRT — MMC_SPI — MMC_RESTO 4. Start the clock 5. Write 0x7b to the MMC_I_MASK register and wait for and verify the MMC_I_REG[END_CMD_RES] interrupt 6. Read the MMC_RES FIFO and MMC_STAT registers Some cards may become busy as the result of a command. The software may wait for the card to become not busy by writing the MMC_I_MASK register and waiting for the MMC_I_REG[PRG_DONE] interrupt or the software can start communication to another card.
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MultiMediaCard Controller The MMC controller performs data transactions in all the basic modes: single block, multiple blocks, and stream modes. 15.3.2.1 Block Data Write In a single block data write, a block of data is written to a card. In a multiple block write, the controller performs multiple single block write data transfers on the MMC bus. After turning the clock on to start the command sequence, the software must program the DMA to fill the MMC_TXFIFO (write 32 bytes).
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MultiMediaCard Controller In a block data read, the following parameters must be specified: • The data transfer is a read. • The block length, if the block length is different from the previous block data transfer or this is the first time that the parameter is being specified. • The number of blocks to be transferred. • The receive data time-out period. The controller will mark the data transaction as timed out if data is not received before the time-out period.
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MultiMediaCard Controller • The data transfer is a read. • The data transfer is in stream mode. • The block length, if the block length is different from the previous block data transfer or this is the first time that the parameter is being specified. • The number of blocks to be transferred as 0xffff. • The receive data time-out period. 15.3.3 Busy Sequence The MMC controller expects a busy signal automatically from the card after every block of data for single and multiple block write operations.
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MultiMediaCard Controller 15.4.1 Start and Stop Clock The set of registers is accessed by stopping the clock, writing the registers, and starting the clock. The software stops the clock, as follows: 1. Write 0x01 in MMC_STRPCL to stop the MMC clock. 2. Write 0x0f in MMC_I_MASK to mask all interrupts except the MMC_I_REG[CLK_IS_OFF] interrupt. 3. Wait for the MMC_I_REG[CLK_IS_OFF] interrupt. To start the clock the software writes 0x02 in MMC_STRPCL. 15.4.
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MultiMediaCard Controller The software must not make changes in the set of registers until the end of the command and response sequence, after the clock is turned on. After the clock is turned on, the software must wait for the MMC_I_REG[END_CMD_RES] interrupt, which indicates that the command and response sequence is finished and the response is in the MMC_RES FIFO. The software may then read the MMC_STAT register to verify the status of the transaction and then read MMC_RES FIFO.
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MultiMediaCard Controller 5. Wait for MMC_I_REG[PRG_DONE] interrupt. This interrupt indicates that the card has finished programming. Software may wait for MMC_I_REG[PRG_DONE] or start another command sequence on a different card. 6. Read the MMC_STAT register to verify the status of the transaction (i.e. CRC error status). To address a different card, the software sends a select command to that card by sending a basic no data command and response transaction.
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MultiMediaCard Controller The multiple block write mode also requires a stop transmission command, CMD12, after the data is transferred to the card. After the MMC_I_REG[DATA_TRAN_DONE] interrupt occurs, the software must program the controller registers to send a stop data transmission command. 15.4.9 Multiple Block Read The multiple block read mode is similar to the single block read mode, except that multiple blocks of data are transferred. Each block is the same length.
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MultiMediaCard Controller 8. Set MMC_I_MASK to 0x1d. 9. Wait for MMC_I_REG[PRG_DONE] interrupt. This interrupt indicates that the card has finished programming. Software may wait for MMC_I_REG[PRG_DONE] interrupt or start another command sequence on a different card. 10. Read the MMC_STAT register to verify the status of the transaction (i.e. CRC error status). To address a different card, the software must send a select command to that card by sending a basic no data command and response transaction.
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MultiMediaCard Controller 15.5 MultiMediaCard Controller Register Descriptions The MMC controller is controlled by a set of registers that software configures before every command sequence on the MMC bus. Table 15-6 lists the address, name, and description of the MMC Controller Registers. Table 15-6 through Table 15-24 describe the registers and FIFOs. Table 15-5. MMC Controller Registers Address 15.5.
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MultiMediaCard Controller Table 15-6. MMC_STRPCL Register Physical Address 4110_0000 MMC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 Bits Name 31:2 — 0 0 0 0 0 0 0 0 0 STRPCL Reserved Bit MMC_STRPCL Register 0 0 0 0 0 0 0 0 0 Description Reserved START/STOP THE MMC CLOCK: 1:0 00 – Do nothing 01 – Stop the MMC clock 10 – Start the MMC clock 11 – Reserved STRPCL 15.5.
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MultiMediaCard Controller Table 15-7.
PAGE 536
MultiMediaCard Controller The software can only write this register after the clock is turned off and the software has received an interrupt that indicates the clock is turned off. Table 15-8.
PAGE 537
MultiMediaCard Controller Table 15-9.
PAGE 538
MultiMediaCard Controller Table 15-10.
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MultiMediaCard Controller Table 15-11. MMC_RESTO Register Physical Address 4110_0014 Bit MMC_RESTO Register MMC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 Reserved Reset 0 0 0 0 0 0 0 0 Bits Name 31:7 — 6:0 0 0 0 0 0 3 2 1 0 0 0 RES_TO 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Description Reserved RESPONSE TIME-OUT: RES_TO 15.5.
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MultiMediaCard Controller 15.5.8 MMC_BLKLEN Register The MMC_BLKLEN register specifies the number of bytes in a block of data. Table 15-13. MMC_BLKLEN Register Physical Address 4110_001c Bit MMC_BLKLEN Register MMC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Reserved Reset 0 0 0 0 0 0 0 0 Bits Name 31:10 — 9:0 0 0 0 4 3 2 1 0 0 0 0 BLK_LEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Reserved BLOCK LENGTH: BLK_LEN 15.5.
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MultiMediaCard Controller Table 15-15. MMC_PRTBUF Register Physical Address 4110_0024 MMC 8 7 6 5 4 3 2 1 Reset 0 0 0 0 0 0 0 Bits Name 31:1 — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF_PART_FULL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved Bit MMC_PRTBUF Register 0 0 0 0 0 0 0 0 Description Reserved BUFFER PARTIALLY FULL: BUF_PART_ 0 – Buffer is not partially full.
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MultiMediaCard Controller Table 15-16.
PAGE 543
MultiMediaCard Controller Table 15-17.
PAGE 544
MultiMediaCard Controller Table 15-18. MMC_CMD Register 8 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved MMC Reserved Bit MMC_CMD Register 0 1 5 4 3 0 0 0 2 1 0 0 0 0 CMD_INDEX Physical Address 4110_0030 Bits Name 31:8 — Reserved 7 — Reserved, read only, always 0. Start bit for command sequence and cannot be changed. 6 — Reserved, read only, always 1.
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MultiMediaCard Controller Table 15-19.
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MultiMediaCard Controller Table 15-19. Command Index Values (Sheet 3 of 3) 15.5.14 CMD INDEX COMM AND MODE 111011 CMD59 SPI 111100 CMD60 MMC Reserved for manufacturer 111101 CMD61 MMC Reserved for manufacturer 111110 CMD62 MMC Reserved for manufacturer 111111 CMD63 MMC Reserved for manufacturer ABBREVIATION CRC_ON_OFF MMC_ARGH Register The MMC_ARGH register specifies the upper 16 bits of the argument for the current command (see Table 15-20). Table 15-20.
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MultiMediaCard Controller 15.5.16 MMC_RES FIFO (read only) The MMC_RES FIFO contains the response after a command. It is 16 bits wide by eight entries.The RES FIFO does not contain the 7-bit CRC for the response. The status for CRC checking and response time-out status is in the status register, MMC_STAT (see Table 15-22). The first half-word read from the response FIFO is the most significant half-word of the received response. Table 15-22.
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MultiMediaCard Controller Table 15-24.
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Network/Audio Synchronous Serial Protocol Serial Ports 16 This chapter describes the signal definitions and operation of the Intel® PXA26x Processor Family Network and Audio Synchronous Serial Protocol (SSP) serial ports. The Network SSP (NSSP) and Audio SSP (ASSP) are similar except for the following: • External pin connections • Memory map base location • The Network ASSP supports swapping the receive and transmit data pins. See Section 4.1, “General-Purpose Input/Output” on page 4-1.
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Network/Audio Synchronous Serial Protocol Serial Ports 16.3 Signal Description Table 16-1 lists the external signals between the SSP serial ports and external device. If any port is disabled, its pins are available for GPIO use. See Section 4.1, “General-Purpose Input/Output” for details on configuring pin direction and Section 4.2, “Interrupt Controller” for Interrupt capabilities. Table 16-1.
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Network/Audio Synchronous Serial Protocol Serial Ports 16.4.1 Processor and DMA FIFO Access The CPU or DMA accesses data through the SSP ports transmit and receive FIFOs. A CPU access takes the form of programmed I/O, transferring one FIFO entry per access. The FIFO are seen as one 32-bit location by the processor. CPU accesses are normally triggered by an SSSR interrupt and are always 32-bits wide.
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Network/Audio Synchronous Serial Protocol Serial Ports 16.4.2.2 Removing Trailing Bytes In this case, no receive DMA service request is generated. To read out the trailing bytes, have the software wait for the time-out interrupt and then read all remaining entries as indicated by SSSR[RFL] and SSSR[RNE]. Note: 16.4.3 The time-out interrupt must be enabled by setting SSCR1[TINTE]. Data Formats Four pins transfer data between the PXA26x processor family and external CODECs or modems.
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Network/Audio Synchronous Serial Protocol Serial Ports • For PSP, the protocol allows for the configuration of which edge of the SSPSCLK is used for switching transmit data and the edge for sampling receive data. In addition, the idle state for SSPSCLK can be controlled and the number of active clocks that precede and follow the data transmission. Master and slave modes are supported. Microwire* uses a half-duplex, master-slave messaging protocol.
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Network/Audio Synchronous Serial Protocol Serial Ports Figure 16-1. Texas Instruments Synchronous Serial Frame* Protocol (multiple transfers) SSPSCLK SSPSFRM SSPTX Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0] SSPRX Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0] A9650-01 Figure 16-2.
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Network/Audio Synchronous Serial Protocol Serial Ports For back-to-back transfers, frames start and complete similar to single transfers, except SSPSFRM does not de-assert between words. Both transmitter and receiver are configured for the word length and internally track the start and end of frames. There are no dead bits; the least significant bit of one frame is followed immediately by the most significant bit of the next.
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Network/Audio Synchronous Serial Protocol Serial Ports The state of SSPRXD is undefined before the MSB and after the LSB is transmitted. For minimum power consumption, this pin must not float. 16.4.3.2.1 Serial Clock Phase (SPH) The phase relationship between the SSPSCLK and the serial frame (SSPSFRM) pins when the Motorola SPI* protocol is selected is controlled by SSCR1[SPH].
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Network/Audio Synchronous Serial Protocol Serial Ports Note: When configured as either master or slave (to clock or frame) the SSP port continues to drive SSPTXD with the last bit of data sent (the LSB). If SSCR0[SSE] is cleared, SSPTXD goes low. The state of SSPRXD is undefined before the MSB and after the LSB is transmitted. For minimum power consumption, this pin must not float. Figure 16-6.
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Network/Audio Synchronous Serial Protocol Serial Ports Figure 16-7. National Semiconductor Microwire* Frame Protocol (multiple transfers) SSPSCLK SSPSFRM Bit[7] or Bit[15] SSPTX/RX Bit[0] SSPTX/RX Undefined Bit[N] Undefined Bit[1] Bit[0] Bit[0] Bit[N] Undefined A9653-01 Note: When configured master the SSP port continues to drive SSPTXD with the last bit of data sent (the LSB) or it drives zero, depending on the status of SSPSP[ETDS]. If SSCR0[SSE] is cleared, SSPTXD goes low.
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Network/Audio Synchronous Serial Protocol Serial Ports clocks programmed in the field SSPSP[SFRMP]. The SSPSFRM remains asserted for the number of half-clocks programmed within SSPSP[SFRMWDTH]. Four to 32-bits can be transferred per frame. Once the LSB transfers, the SSPSCLK continues toggling based on the dummy stop field (SSPSP[DMYSTOP]).
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Network/Audio Synchronous Serial Protocol Serial Ports Figure 16-10. Programmable Serial Protocol (single transfers) SSPSCLK (when SCMODE = 0) SSPSCLK (when SCMODE = 1) SSPSCLK (when SCMODE = 2) SSPSCLK (when SCMODE = 3) Undefined SSPTXD T1 SSPRXD MSB LSB T2 T3 Undefined End of Transfer Data State T4 MSB LSB Undefined SSPSFRM (when SFRMP = 1) SSPSFRM T5 T6 (when SFRMP = 0) A9522-02 Table 16-2.
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Network/Audio Synchronous Serial Protocol Serial Ports (SSCR1[SFRMDIR] is set) if the assertion of frame is not before the MSB is sent (For example, T5 <= T2 if SSCR1[SFRMDIR] is set). Transmit Data transitions from the “End of Transfer Data State” to the next MSB value upon the assertion of frame. The start delay field should be programmed to 0 whenever SSPSCLK or SSPSFRM is configured as an input. 16.4.
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Network/Audio Synchronous Serial Protocol Serial Ports Figure 16-12. TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=1 SSPSCLK SSPSFRM SSPTXD SSPRXD Undefined Bit[N] Bit[N-1] Bit[1] Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0] MSB 4 to 32 Bits Undefined LSB A9975-01 Note: 16.4.4.2 If SSPSCLK is an input, the device driving SSPSCLK must provide another clock edge to cause the TXD line to go to Hi-Z. Motorola SPI When SSCR1[TTE] is 0, the SSP behaves as described in Section 16.4.3.2.
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Network/Audio Synchronous Serial Protocol Serial Ports Figure 16-14. National Semiconductor Microwire with SSCR1[TTE]=1 SSPSCLK SSPSFRM Bit[7] or Bit[15] SSPTXD Bit[0] 8 or 16-Bit Control Undefined SSPRXD Bit[N] Undefined Undefined Bit[0] 4 to 32 Bits A9977-01 Note: 16.4.4.4 SSCR1[TTELP] must be 0 for National Semiconductor Microwire. Programmable Serial Protocol When SSCR1[TTE] is 0, the SSP behaves as described in Section 16.4.3.4.
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Network/Audio Synchronous Serial Protocol Serial Ports Figure 16-16. PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (master to frame) SSPSCLK (when SCMODE = 0) SSPSCLK (when SCMODE = 1) SSPSCLK (when SCMODE = 2) SSPSCLK (when SCMODE = 3) SSPTXD MSB T1 T2 Undefined SSPRXD LSB T3 T4 LSB MSB Undefined SSPSFRM (when SFRMP = 1) T5 SSPSFRM T6 (when SFRMP = 0) A9979-01 SSCR1[TTELP] can only be set to 1 in PSP mode if the SSP is a slave to frame.
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Network/Audio Synchronous Serial Protocol Serial Ports 16.4.5 FIFO Operation Two separate and independent FIFOs are present for transmit (to peripheral) and receive (from peripheral) serial data. FIFOs are filled or emptied by programmed I/O or DMA bursts. 16.4.5.1 Using Programmed I/O Data Transfers The PXA26x processor family can perform FIFO filling and emptying in response to an interrupt from the FIFO logic. Each FIFO has a programmable trigger threshold at which an interrupt is triggered.
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Network/Audio Synchronous Serial Protocol Serial Ports 16.5 SSP Port Register Descriptions Each SSP port consists of seven registers: three control, one data, one status, one time-out, and one test. • The SSP control registers (SSCR0, SSCR1) configure the baud rate, data length, frame format, data-transfer mechanism, and port enabling. They also permit setting the FIFO trigger threshold that triggers an interrupt. • Access all registers using aligned words.
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Network/Audio Synchronous Serial Protocol Serial Ports Table 16-3.
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Network/Audio Synchronous Serial Protocol Serial Ports Table 16-3.
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Network/Audio Synchronous Serial Protocol Serial Ports 16.5.2 SSP Control Register 1 (SSCR1) SSCR1, shown in Table 16-4, contains bit fields that control various SSP port functions. Before enabling the port (using SSCR0[SSE]), the desired values for this register must be set. These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits. Table 16-4.
PAGE 570
Network/Audio Synchronous Serial Protocol Serial Ports Table 16-4.
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Network/Audio Synchronous Serial Protocol Serial Ports Table 16-4.
PAGE 572
Network/Audio Synchronous Serial Protocol Serial Ports Table 16-4.
PAGE 573
Network/Audio Synchronous Serial Protocol Serial Ports Table 16-4.
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Network/Audio Synchronous Serial Protocol Serial Ports Table 16-4.
PAGE 575
Network/Audio Synchronous Serial Protocol Serial Ports 16.5.3 SSP Programmable Serial Protocol Register (SSPSP) SSPSPx, shown in Table 16-5, contains bit fields used to program the various programmable serialprotocol parameters. The contents of these registers are ignored if the PSP is not selected. These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits. Table 16-5.
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Network/Audio Synchronous Serial Protocol Serial Ports Table 16-5.
PAGE 577
Network/Audio Synchronous Serial Protocol Serial Ports Table 16-6.
PAGE 578
Network/Audio Synchronous Serial Protocol Serial Ports Table 16-7.
PAGE 579
Network/Audio Synchronous Serial Protocol Serial Ports Table 16-8.
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Network/Audio Synchronous Serial Protocol Serial Ports Table 16-8.
PAGE 581
Network/Audio Synchronous Serial Protocol Serial Ports Table 16-8.
PAGE 582
Network/Audio Synchronous Serial Protocol Serial Ports 16.5.7 SSP Data Register (SSDR) SSDR, shown in Table 16-9, is a single address location that read and write data transfers access. SSDR represents two physical registers: the first is temporary storage for data on its way out through the transmit FIFO. The other register is temporary storage for data coming in through the receive FIFO.
PAGE 583
Network/Audio Synchronous Serial Protocol Serial Ports Table 16-10. NSSP Register Address Map Physical Address Name Description 0x4140 0000 NSSCR0 NSSP Control register 0 0x4140 0004 NSSCR1 NSSP Control register 1 0x4140 0008 NSSSR NSSP Status register 0x4140 000C NSSITR NSSP Interrupt Test register 0x4140 0010 NSSDR NSSP Data Write Register / Data Read register 0x4140 0028 NSSTO NSSP Time Out register 0x4140 002C NSSPSP NSSP Programmable Serial Protocol Table 16-11.
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Network/Audio Synchronous Serial Protocol Serial Ports 16-36 Intel® PXA26x Processor Family Developer’s Manual
PAGE 585
Hardware UART 17 This chapter describes the signal definitions and operation of the Intel® PXA26x Processor Family Hardware UART (HWUART) port. The HWUART interface pins are available via either the PCMCIA general purpose I/O (GPIO) pins or the BTUART pins. When using the HWUART through the PCMCIA pins, they are driven at the same voltage level as the memory interface.
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Hardware UART 17.2 Features The HWUART has the following features: • Functionally compatible with the 16550A and 16750 UART specifications.
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Hardware UART • Slow infrared asynchronous interface that conforms to the Infrared Data Association (IrDA) standard 17.3 Signal Descriptions Table 17-1 lists and describes each external signal that is connected to the UART module. The pins are connected to the PXA26x processor family through GPIOs. Refer to Section 4.1, “GeneralPurpose Input/Output” for details on the GPIOs. Table 17-1.
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Hardware UART Figure 17-1. Example UART Data Frame Start Data Data Data Data Data Data Data Data Bit <0> <1> <2> <3> <4> <5> <6> <7> Parit y Bit Stop Stop Bit 1 Bit 2 TXD or RXD pin MSB LSB Receive data sample counter frequency is 16 times the value of the bit frequency. The 16X clock is created by the baud rate generator. Each bit is sampled three times in the middle. Shaded bits in Figure 17-1 are optional and can be programmed by software.
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Hardware UART 17.4.1 Reset The UART is disabled on reset. To enable the UART, software must program the GPIO registers (see Section 4.1, “General-Purpose Input/Output”) then set IER[UUE]. When the UART is enabled, the receiver waits for a frame start bit and the transmitter sends data if it is available in the Transmit Holding Register. Transmit data can be written to the Transmit Holding Register before the UART unit is enabled.
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Hardware UART 17.4.2.1.3 Transmit Interrupt Transmit interrupts can only occur when the transmit FIFO and transmit interrupt are enabled. The transmit data request interrupt occurs when the transmit FIFO is at least half empty. The interrupt is cleared when the THR is written or the IIR is read. 17.4.2.2 FIFO Polled Mode Operation When the FIFOs are enabled, clearing both IER[DMAE] and IER[4:0] places the serial port in FIFO polled operating mode.
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Hardware UART Note: When DMA requests are enabled and an interrupt occurs, software must first read the LSR to see if an error interrupt exists, then check the IIR for the source of the interrupt. If an interrupt occurs and LSR[FIFOE] is clear, software must read the ISR to determine the error condition. When the last error byte is read from the FIFO, DMA requests are automatically enabled.
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Hardware UART When in Full or Half-Autoflow mode, nCTS is asserted by the remote receiver when the receiver is ready to receive data from the UART. The UART checks nCTS before sending the next byte of data and will not transmit the byte until nCTS is low. If nCTS goes high while the transfer of a byte is in progress, the transmitter will complete this byte. Note: 17.4.4 Autoflow mode can be used only in conjunction with FIFO mode. Auto-Baud-Rate Detection The HWUART supports auto-baud-rate detection.
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Hardware UART The SIR interface does not contain the actual IR LED driver or the receiver amplifier. The I/O pins attached to the SIR only have digital CMOS level signals. The SIR supports two-way communication, but full duplex communication is not possible because reflections from the transmit LED enter the receiver. The SIR interface supports frequencies up to 115.2 Kbps. Because the input clock is 14.7456 MHz, the baud divisor must be eight or more. 17.4.5.
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Hardware UART Figure 17-4. XMODE Example. 1 16X Baud Clock 7 11 16 Transmit Start bit followed by 1 IR_TXD Pin value XMODE = 0 3 16X BAUD Clock periods IR_TXD Pin value XMODE = 1 1.6 µs Note: The SIR TXD output pin is automatically held deasserted when the RCVEIR bit is set. Before setting the RCVEIR bit, check that the TEMT bit is 1. While receiving, any data placed in the transmit FIFO will not be held. Only add data to the transmit FIFO while not receiving.
PAGE 595
Hardware UART Table 17-2. RBR Bit Definitions Physical Address 0x4160 0000 (DLAB=0) PXA26x Processor Family Hardware UART Read Buffer Reg. (RBR) User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 Reserved Reset ? ? ? ? ? ? ? ? ? ? ? Bits Access 31:8 N/A — 7:0 R Byte 0 17.5.2 ? ? ? 4 3 2 1 0 0 0 0 Byte 0 ? ? ? ? ? ? Name ? ? ? ? 0 0 0 0 0 Description Reserved – Read as unknown and must be written as zero.
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Hardware UART Load these divisor latches during initialization to ensure that the baud rate generator operates properly. If each divisor latch is loaded with a 0, the 16X clock stops. The divisor latches are accessed with a word write. The baud rate of the data shifted in to or out of a UART is given by the formula: 14.7456 MHz BaudRate = ---------------------------------( 16xDivisor ) For example, if the divisor is 24, the baud rate is 38400 bps. The divisor’s reset value is 0x0002.
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Hardware UART 17.5.4 Interrupt Enable Register (IER) The IER enables the five types of interrupts that set a value in the Interrupt Identification Register (IIR). To disable an interrupt, software must clear the appropriate bit in the IER. Software can enable some interrupts by setting the appropriate bit. The Character Timeout Indication interrupt is separated from the received data available interrupt to ensure that the processor and the DMA controller do not service the receive FIFO at the same time.
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Hardware UART Table 17-6. IER Bit Definitions (Sheet 2 of 2) Physical Address 0x4160_0004 PXA26x Processor Family Hardware UART Interrupt Enable Reg.
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Hardware UART Table 17-7. Interrupt Conditions Priority Level 1 (highest) Interrupt origin Receiver line status – one or more error bits were set. 2 Received data is available – In FIFO mode, trigger threshold was reached. In non-FIFO mode, RBR has data. 2 Receiver timeout occurred – Occurs only in FIFO mode, when data is in the receive FIFO but no data has been sent for a set time period. 3 Transmitter requests data – In FIFO mode, the transmit FIFO is at least half empty.
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Hardware UART Table 17-8. IIR Bit Definitions (Sheet 2 of 2) Physical Address 0x4160_0008 PXA26x Processor Family Hardware UART Interrupt Identification Reg. (IIR) ? ? ? ? ? Bits ? ? ? ? ? Access 3 ? ? ? ? 0 ? ? ? ? ? ? Name R 5 ? ? ? 4 3 0 ? 0 0 2 1 0 0 1 nIP ? Reserved Reset 6 IID 7 ABL 8 TOD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 FIFOES Bit Reserved User Settings 0 Description TIME OUT DETECTED (See Section 17.4.2.
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Hardware UART Table 17-9. Interrupt Identification Register Decode (Sheet 2 of 2) Interrupt ID bits Interrupt SET/RESET Function 3 2 1 0 Priority Type Source RESET Control Reading the IIR (if the source of the interrupt) or writing into the Transmit Holding Register. Non-FIFO mode – Transmit Holding Register Empty IID[01] 0 0 1 0 IID[00] 0 0 0 0 Third Highest Transmit FIFO Data Request Fourth Highest Clear to Send, Data Set Ready, Ring Modem Status Indicator, Received Line Signal Detect.
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Hardware UART Table 17-10. FCR Bit Definitions (Sheet 2 of 2) Physical Address 0x4160_0008 PXA26x Processor Family Hardware UART FIFO Control Reg.
PAGE 603
Hardware UART All reserved bits are read as unknown and must be written with a 0. The register organization and the individual bit definitions are shown in Table 17-11 on page 17-19. Table 17-11. FOR Bit Definitions Physical Address 0x4160_0024 PXA26x processor family Hardware UART FIFO Occupancy Reg. (FOR) User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 Reserved Reset ? 17.5.
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Hardware UART Note: Auto-baud rate detection is not supported with slow infrared Mode. Table 17-12. ABR Bit Definitions Physical Address 0x4160_0028 PXA26x processor family Hardware UART Autobaud Control Reg.
PAGE 605
Hardware UART Table 17-13. ACR Bit Definitions Physical Address 0x4160_002C PXA26x Processor Family Hardware UART Autobaud Count Reg. (ACR) User Settings Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved Reset ? ? ? ? ? ? ? ? ? ? ? Access Name 31:16 N/A — 17.5.
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Hardware UART Table 17-14. LCR Bit Definitions (Sheet 1 of 2) Physical Address 0x4160_000C PXA26x Processor Family Hardware UART Line Control Reg.
PAGE 607
Hardware UART Table 17-14. LCR Bit Definitions (Sheet 2 of 2) Physical Address 0x4160_000C PXA26x Processor Family Hardware UART Line Control Reg.
PAGE 608
Hardware UART See Section 17.4.2.3, “FIFO DMA Mode Operation” for details on using the DMA to receive data. Table 17-15. LSR Bit Definitions (Sheet 1 of 3) Physical Address 0x4160_0014 PXA26x Processor Family Hardware UART Line Status Reg.
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Hardware UART Table 17-15. LSR Bit Definitions (Sheet 2 of 3) Physical Address 0x4160_0014 PXA26x Processor Family Hardware UART Line Status Reg.
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Hardware UART Table 17-15. LSR Bit Definitions (Sheet 3 of 3) Physical Address 0x4160_0014 PXA26x Processor Family Hardware UART Line Status Reg.
PAGE 611
Hardware UART Table 17-16. MCR Bit Definitions (Sheet 1 of 2) Physical Address 0x4160_0010 PXA26x Processor Family Hardware UART Modem Control Reg.
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Hardware UART Table 17-16. MCR Bit Definitions (Sheet 2 of 2) Physical Address 0x4160_0010 PXA26x Processor Family Hardware UART Modem Control Reg.
PAGE 613
Hardware UART Note: When bit 0, 1, 2, or 3 is set, a Modem Status interrupt is generated if IER[MIE] is set. Table 17-17. MSR Bit Definitions Physical Address 0x4160_0018 PXA26x Processor Family Hardware UART Modem Status Reg. (MSR) User Settings 7 6 5 4 ? ? ? ? 1 Reserved Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 3 ? ? ? ? ? ? ? ? Bits Access Name 31:8 N/A — Reserved – Read as unknown and must be written as zero.
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Hardware UART 17.5.15 Infrared Selection Register (ISR) Each UART can manage an IrDA module associated with it. The Infrared Selection Register controls IrDA functions (see Section 17.4.5, “Slow Infrared Asynchronous Interface” on page 17-8). The ISR bit definitions are shown in Table 17-19. Table 17-19. ISR Bit Definitions (Sheet 1 of 2) Physical Address 0x4160_0020 PXA26x Processor Family Hardware UART Infrared Selection Reg.
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Hardware UART Table 17-19. ISR Bit Definitions (Sheet 2 of 2) Physical Address 0x4160_0020 PXA26x Processor Family Hardware UART Infrared Selection Reg.
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Hardware UART Table 17-20.
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18 Internal Flash This chapter describes the flash interface for the Intel® PXA26x Processor Family. The PXA26x processor family has three devices that contain internal Intel StrataFlash® memory: • PXA261 processor – 128 megabit x 16 Intel StrataFlash® memory • PXA262 processor – 256 megabit x 16 Intel StrataFlash® memory • PXA263 processor – 256 megabit x 32 Intel StrataFlash® memory For the best performance, configure one of the PXA26x processor family devices (in the list above) in synchronous mode.
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Internal Flash If watchdog reset is not necessary, a secondary GPIO can control nRESET_OUT using the equation nRST_F = nRESET & (nRESET_OUT | GPIO_a). This allows sleep-mode entry to reset the flash memory while keeping it in synchronous mode during a GPIO reset. Figure 18-2 shows the required logic. GPIO_a is an unused GPIO that is kept high during normal operation and driven low before sleep-mode entry and held low during sleep mode. Figure 18-2.
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Internal Flash Table 18-1. SXCNFG Configuration for Internal Flash Memory Clock SDCLK[0] Frequency Frequency SXCNFG SXLATCH 0 SXTP0 SXCA0 SXRA0 SXRL0 SXCL0 SXEN0 100 MHz 50 MHz 0xXXXX 60F1 1 0b10 0 0 0b111 0b100 0b01 133 MHz 66 MHz 0xXXXX 60F9 1 0b10 0 0 0b111 0b110 0b01 Warning: 18.1.5 Using a memory-clock frequency above 133 MHz is not allowed in synchronous mode with Intel StrataFlash® memory.
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Internal Flash ;//--- Configure the processor in synchronous mode ;//--- Can be used with normal K3, ensure bus width check is for correct chip select ;//--- Read the CCCR to check the memory clock frequency LDR r3,=CCCR LDR r4,[r3] AND r4, r4, #0x1F ;/* First 5 bits = L value */ ldr r1, =0x0 cmp r4, #0x1 ldreq r1, =0x1 cmp r4, #0x2 ldreq r1, =0x2 cmp r4, #0x3 ldreq r1, =0x2 cmp r4, #0x4 ;/* Default to Asynchronous mode */ ;/* Memory Frequency = 100 MHz */ ;/* Memory Frequency = 118 MHz (Use 133 MHz setti
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Internal Flash ;//--- Fill up registers with correct values -- 50 MHz SDCLK0_50MHz ;//--- Check for 16/32 bit mode ldr r3, =MSC0 ldr r3, [r3] and r3, r3, #0x8 cmp r3, #0x8 beq SDCLK0_50MHz_16bit ;//--- Configure for 50 MHz/32 bit operation ldr r3, =SXCNFG ldr r4, =0x00009708 ldr r5, =0x00600060 ldr r6, =0x00030003 ldr r7, =0x60f1 b aligned_address_32 SDCLK0_50MHz_16bit ldr r3, =SXCNFG ldr r4, =0x00004b84 ldr r5, =0x0060 ldr r6, =0x0003 ldr r7, =0x60f1 b aligned_address_16 ;//--- Send out values to register
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Internal Flash strh r9, [r8] ;/* No need for cache alignment since second flash chip */ ldrh r9, [r8] ;/* Read identifier second bus cycle, address=0x0 */ cmp r9, #0x89 ;/* Intel manufacturer code */ bne EndSynchronousMode ;//--- Write to second 128 Mbit flash.
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Internal Flash Intel® PXA26x Processor Family Developer’s Manual 18-7
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