Laptop User Manual

4-12 Intel® PXA26x Processor Family Developer’s Manual
System Integration Unit
Table 4-11. GPSR2 Register Bitmap
Physical Address
0x40E0_0020
GPIO Pin Output Set Register2
(GPSR2)
System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
PS89 PS88 PS87 PS86 PS85 PS84 PS83 PS82 PS81 PS80 PS79 PS78 PS77 PS76 PS75 PS74 PS73 PS72 PS71 PS70 PS69 PS68 PS67 PS66 PS65 PS64
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
<31:26> — Reserved
<25:0> PS[x]
GPIO Pin ‘x’ Output Pin Set (where x = 64 through 89).
0 – Pin level unaffected.
1 – If pin configured as an output, set pin level high (one).
Table 4-12. GPCR0 Bit Definitions
Physical Address
0x40E0_0024
GPCR0 System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC31 PC30 PC29 PC28 PC27 PC26 PC25 PC24 PC23 PC22 PC21 PC20 PC19 PC18 PC17 PC16 PC15 PC14 PC13 PC12
PC11
PC10
PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
<31:0> PC[x]
GPIO Pin ‘x’ Output Pin Clear (where x = 0 through 31).
0 – Pin level unaffected.
1 – If pin configured as an output, clear pin level low (zero).
Table 4-13. GPCR1 Bit Definitions
Physical Address
0x40E0_0028
GPCR1 System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC63 PC62 PC61 PC60 PC59 PC58 PC57 PC56 PC55 PC54 PC53 PC52 PC51 PC50 PC49 PC48 PC47 PC46 PC45 PC44 PC43 PC42 PC41 PC40 PC39 PC38 PC37 PC36 PC35 PC34 PC33 PC32
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
<31:0> PC[x]
GPIO Pin ‘x’ Output Pin Clear (where x = 32 through 63).
0 – Pin level unaffected.
1 – If pin configured as an output, clear pin level low (zero).