Laptop User Manual

Intel® PXA26x Processor Family Developer’s Manual 4-17
System Integration Unit
4.1.3.6 GPIO Alternate Function Register (GAFR)
The GPIO alternate function registers (GAFR2, GAFR1, GAFR0) contain select bits that
correspond to the 90 GPIO pins. Each GPIO can be configured to be either a generic GPIO pin, one
of 3 alternate input functions, or one of 3 alternate output functions. To select any of the alternate
input functions, the GPDR register must configure the GPIO to be an input. Similarly, only GPIOs
configured as outputs by the GPDR can be configured for alternate output functions. Each GPIO
pin has a pair of bits assigned to it whose values determine which function (normal GPIO, alternate
function 1, alternate function 2 or alternate function 3) the GPIO performs. The function selected is
determined by writing the GAFR bit pair as below:
Table 4-22. GEDR1 Bit Definitions
Physical Address
0x40E0_004C
GEDR1 System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ED63 ED62 ED61 ED60 ED59 ED58 ED57 ED56 ED55 ED54 ED53 ED52 ED51 ED50 ED49 ED48 ED47 ED46 ED45 ED44 ED43 ED42 ED41 ED40 ED39 ED38 ED37 ED36 ED35 ED34 ED33 ED32
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
<31:0> ED[x]
GPIO PIN ‘X’ EDGE DETECT STATUS (where x = 32 through 63):
READ
0 – No edge detect has occurred on pin as specified in GRER or GFER.
1 – Edge detect has occurred on pin as specified in GRER or GFER.
WRITE
0 – No effect.
1 – Clear edge detect status field.
Table 4-23. GEDR2 Register Bitmap
Physical Address
0x40E0_0050
GPIO Edge Detect Status
Register2 (GEDR2)
System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
ED89 ED88 ED87 ED86 ED85 ED84 ED83 ED82 ED81 ED80 ED79 ED78 ED77 ED76 ED75 ED74 ED73 ED72 ED71 ED70 ED69 ED68 ED67 ED66 ED65 ED64
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
<31:26> — Reserved
<25:0> ED[x]
GPIO PIN ‘X’ EDGE DETECT STATUS (where x = 64 through 89):
READ
0 – No edge detect has occurred on pin as specified in GRER or GFER.
1 – Edge detect has occurred on pin as specified in GRER or GFER.
WRITE
0 – No effect.
1 – Clear edge detect status field.