Laptop User Manual

3-6 Intel® PXA26x Processor Family Developer’s Manual

Clocks and Power Manager

3.3.5 147.46-MHz Peripheral Phase Locked Loop

The 147.46-MHz PLL is the clock source for many of the peripheral blocks’ external interfaces.

These interfaces require: ~14.75 MHz for the UARTs, 12.288 MHz for the AC97, and variable

frequencies for I

S. The generated frequency may not exactly match the required frequency due to

the choice of crystal and the lack of a perfect least common multiple between the units. The chosen

frequencies keep each unit’s clock frequency within the unit’s clock tolerance. If a crystal other

than 3.6864 MHz is used, the clock frequencies to the peripheral blocks’ interfaces may not yield

the desired baud rates (or other protocol’s rate)

3.3.6 Clock Gating

The clocks manager contains the CKEN register. This register contains configuration bits that can

disable the clocks to individual units. The configuration bits are used when a module is not being

used. After a hardware reset, any module that is not being used must have its clock disabled. If a

module is temporarily quiescent but does not have clock gating functionality, use the CKEN

When a module’s clock is disabled, the registers in that module are still readable and writable. The

AC97 is an exception and is completely inaccessible if the clock is disabled.

3.4 Resets and Power Modes

The clocks and power manager unit determines the processor’s resets, power sequences and power

modes. Each behaves differently during operation and has specific entry and exit sequences. The

resets and power modes are:

• Hardware reset

• Watchdog reset

• GPIO reset

• Run mode

• Turbo mode

• Idle mode

• Frequency change sequence

• Sleep mode

Table 3-3. 147.46-MHz Peripheral PLL Output Frequencies for 3.6864-MHz Crystal

Unit Name Nominal Frequency Actual Frequency

UARTs 14.746 MHz 14.746 MHz

AC97 12.288 MHz 12.288 MHz

S 146.76 MHz 147.46 MHz