Datasheet

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Mobile Intel

Celeron

Processor (0.13 µ) in

Micro-FCBGA and Micro-FCPGA Packages

At 1.33 GHz, 1.26 GHz, 1.20 GHz, 1.13 GHz, 1.06

GHz,1.00 GHz; Low Voltage 866 MHz, 733 MHz,

650 MHz; and Ultra Low Voltage 800 MHz, 733

MHz, 700 MHz, and 650 MHz

Datasheet

April 2003

Order Number: 298517-006

Summary of content (98 pages)

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R Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages At 1.33 GHz, 1.26 GHz, 1.20 GHz, 1.13 GHz, 1.06 GHz,1.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Contents 1. Introduction .................................................................................................................................10 1.1 1.2 1.3 1.4 2. Mobile Intel Celeron Processor Features ...................................................................................13 2.1 2.2 2.3 2.4 3. New Features in the Mobile Intel Celeron Processor ............................................
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet 3.6 4. System Signal Simulations......................................................................................................... 58 4.1 4.2 4.3 5. Thermal Diode............................................................................................................... 82 Processor Initialization and Configuration.................................................................................. 83 7.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Figures Figure 1. Clock Control States................................................................................................. 15 Figure 2. PLL RLC Filter.......................................................................................................... 23 Figure 3. VTTPWRGD System-Level Connections................................................................. 24 Figure 4. Noise Estimation ..........
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Tables Table 1. New and Revised Mobile Intel Celeron Processor (0.13 µ) Signals .......................... 14 Table 2. Clock State Characteristics........................................................................................ 17 Table 3. Mobile Intel Celeron Processor CPUID...................................................................... 18 Table 4.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 42. VTTPWRGD Transition Parameter Recommendation............................................ 63 Table 43. Socketable Micro-FCPGA Package Specification................................................... 65 Table 44. Micro-FCBGA Package Mechanical Specifications................................................. 69 Table 45. Signal Listing in Order by Pin/Ball Number ...................................................
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Revision History Date Revision Updates October 2001 298517-001 Initial release January 2002 298517-002 Updates include: • Added new processor speeds 1.2 GHz, 1.13 GHz, and 1.06 GHz at 1.45V. • Added new Low Voltage 667 MHz • Added new Ultra Low Voltage 650 MHz • Updated Processor Specifications (Tables 9, 12-15, 40) • Added Specification Clarification for VTTPWRGD in Table 25, Figure 21 and Section 4.3.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and MicroFCPGA Packages Product Features 298517-006 Mobile Intel® Celeron® Processor with the following Processor core/bus speeds:  1.333 GHz/133 MHz at 1.50 V  1.200 GHz/133 MHz at 1.45 V  1.133 GHz/133 MHz at 1.45 V  1.066 GHz/133 MHz at 1.45 V  1.266 GHz/133 MHz at 1.40 V  1.000 GHz/133 MHz at 1.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet 1. Introduction Using Intel’s advanced 0.13-micron process technology with copper interconnect, the Mobile Intel Celeron Processor offers high-performance and low-power consumption. The Mobile Intel Celeron Processor (0.13µ) in Micro-FCBGA and Micro-FCPGA packages (hereafter referred to as “the Mobile Intel Celeron Processor”) is based on the same core as existing mobile Intel® Pentium® III Processor-M.
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Mobile Intel® Celeron® Processor (0.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet 1.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet 2. Mobile Intel Celeron Processor Features 2.1 New Features in the Mobile Intel Celeron Processor 2.1.1 133-MHz PSB With AGTL Signaling The Mobile Intel Celeron Processor uses Assisted GTL (AGTL) signaling on the PSB interface. The main difference between AGTL and GTL+ used on previous Intel processors is VCCT = 1.25 V for AGTL versus 1.5 V for GTL+. The lower voltage swing enables high performance at lower power.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet 2.1.5 Signal Differences Between the Mobile Intel Celeron Processor (0.18 µ) (in BGA2 and Micro-PGA2 Packages) and the Mobile Intel Celeron Processor (0.13 µ) (in Micro-FCBGA and MicroFCPGA Packages) A list of new and changed signals is shown in Table 1. Table 1. New and Revised Mobile Intel Celeron Processor (0.13 µ) Signals Signals BCLK, BCLK# Function Differential host clk signals.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Asserting the STPCLK# signal while in the Auto Halt state will cause the processor to transition to the Quick Start state. Deasserting STPCLK# will cause the processor to return to the Auto Halt state without issuing a new Halt bus cycle. The SMI# interrupt is recognized in the Auto Halt state. The return from the System Management Interrupt (SMI) handler can be to either the Normal state or the Auto Halt state.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet A transition to the Deep Sleep state can be made by stopping the clock input to the processor or asserting the DPSLP# signal. A transition back to the Normal state (from the Quick Start state) is made only if the STPCLK# signal is deasserted. While in this state the processor is limited in its ability to respond to input.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 2. Clock State Characteristics Clock State Exit Latency Snooping? System Uses Normal N/A Yes Normal program execution Auto Halt 10 µsec Yes S/W controlled entry idle mode Quick Start Through snoop, to HALT/Grant Snoop state: immediate Yes H/W controlled entry/exit mobile throttling Through STPCLK#, to Normal state: 10 µsec 2.2.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 3. Mobile Intel Celeron Processor CPUID EAX[31:0] EBX[7:0] Reserved [31:14] Type [13:12] Family [11:8] Model [7:4] Stepping [3:0] X 6 B X 0 Brand ID 07 Table 4.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet 3. Electrical Specifications 3.1 Processor System Signals Table 5 lists the processor system signals by type. All AGTL signals are synchronous with the BCLK and BCLK# signals. All TAP signals are synchronous with the TCK signal except TRST#. All CMOS input signals can be applied asynchronously. Table 5.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 6. Recommended Resistors for Mobile Intel Celeron Processor Signals Recommended Resistor Value (Ω) Mobile Intel Celeron Processor Signal 10 pull-down BREQ0# 14 pull-up NCTRL 1, 2 3 39 pull-up TMS 39 pull-down TCK 56.2 pull-up PRDY#, RESET# 56.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet other 1.5-V JTAG specification compliant devices be last in the JTAG chain after any devices with 3.3V or 5.0-V JTAG interfaces within the system. A translation buffer should be used to reduce the TDO output voltage of the last 3.3/5.0 V device down to the 1.5-V range that the Mobile Intel Celeron Processor can tolerate. Multiple copies of TMS and TRST# must be provided, one for each voltage level.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet The Open-drain output signals have open drain drivers and external pull-up resistors are required. One of the two output signals (IERR#) is a catastrophic error indicator and is tri-stated (and pulled-up) when the processor is functioning normally. The FERR# output can be either tri-stated or driven to VSS when the processor is in a low-power state depending on the condition of the floating-point unit.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet section. PLL1 and PLL2 should be connected according to Figure 2. Do not connect PLL2 directly to VSS. Appendix A contains the RLC filter specification. Figure 2. PLL RLC Filter L1 R1 PLL1 VCCT C1 PLL2 3.2.3 V0027-01 Voltage Identification There are five voltage identification balls/pins on the Mobile Intel Celeron Processor. These signals can be used to support automatic selection of VCC voltages.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 3. VTTPWRGD System-Level Connections Vcct Vcct Processor Voltage Regulator 1k Vcct Vttpwrgd (output) Vttpwrgd (input) 3.3V 100k 10k Clock Generator Vttpwrgd# (input) 1.2V to 3.3V Level Shifter 3.2.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet 3.2.4.3 Noise The signal quality of the VTTPWRGD signal is critical to the correct operation of the processor. Every effort should be made to ensure this signal is monotonic in the transition region. If noise or glitches are present on this signal, it must be kept to less than 100 mV of a voltage drop from the highest voltage level received to that point.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet 3.4 Maximum Ratings Table 10 contains the Mobile Intel Celeron Processor stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. The processor should not receive a clock while subjected to these conditions. Functional operating conditions are provided in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 11. Power Specifications for Mobile Intel Celeron Processor1 Symbol VCC VCC,DC VCCT Parameter Min Transient VCC for core logic Static VCC for core logic Typ Max Unit Notes 1.10 1.15 1.40 1.45 1.50 V V V V V Note 11 Notes 9, 10 Notes 9, 10 Notes 9, 10 Notes 9, 10 1.10 1.15 1.40 1.45 1.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet 4. ICCx,max specifications are specified at VCC static (typical) derived from the tolerances in Table 12 through Table 19, VCCT,max, Tjmax, and under maximum signal loading conditions. 5. Based on simulations and averaged over the duration of any change in current. Use to compute the maximum inductance and reaction time of the voltage regulator. This parameter is not tested. 6.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 13. VCC Tolerances for the Low Voltage Mobile Intel Celeron Processor in the Deep Sleep State: VID = 1.15 V VCC (V) ICC (A) Static Transient Typ Min Max Min Max 0.0 1.114 1.089 1.139 1.069 1.159 1.0 1.110 1.085 1.135 1.065 1.155 2.0 1.106 1.081 1.131 1.061 1.151 3.0 1.102 1.077 1.127 1.057 1.147 4.0 1.098 1.073 1.123 1.053 1.143 5.0 1.094 1.069 1.119 1.049 1.139 6.0 1.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 15. VCC Tolerances for the Ultra Low Voltage Mobile Intel Celeron Processor in the Deep Sleep State: VID = 1.1 V VCC (V) ICC (A) 30 Static Transient Typ Min Max Min Max 0.0 1.068 1.043 1.093 1.023 1.113 1.0 1.064 1.039 1.089 1.019 1.109 2.0 1.060 1.035 1.085 1.015 1.105 3.0 1.056 1.031 1.081 1.011 1.101 4.0 1.052 1.027 1.077 1.007 1.097 5.0 1.048 1.023 1.073 1.003 1.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 16. VCC Tolerances for the Mobile Intel Celeron Processor: VID = 1.40 V VCC (V) ICC (A) 298517-006 Static Transient Typ Min Max Min Max 0.0 1.400 1.375 1.425 1.355 1.445 1.0 1.396 1.371 1.421 1.351 1.441 2.0 1.392 1.367 1.417 1.347 1.437 3.0 1.388 1.363 1.413 1.343 1.433 4.0 1.384 1.359 1.409 1.339 1.429 5.0 1.380 1.355 1.405 1.335 1.425 6.0 1.376 1.351 1.401 1.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 17. VCC Tolerances for the Mobile Intel Celeron Processor in the Deep Sleep State: VID = 1.40 V VCC (V) ICC (A) 32 Static Transient Typ Min Max Min Max 0.0 1.338 1.313 1.363 1.293 1.383 1.0 1.334 1.309 1.359 1.289 1.379 2.0 1.330 1.305 1.355 1.285 1.375 3.0 1.326 1.301 1.351 1.281 1.371 4.0 1.322 1.297 1.347 1.277 1.367 5.0 1.318 1.293 1.343 1.273 1.363 6.0 1.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 18. VCC Tolerances for the Mobile Intel Celeron Processor: VID = 1.45 V VCC (V) ICC (A) 298517-006 Static Transient Typ Min Max Min Max 0.0 1.450 1.425 1.475 1.405 1.495 1.0 1.446 1.421 1.471 1.401 1.491 2.0 1.442 1.417 1.467 1.397 1.487 3.0 1.438 1.413 1.463 1.393 1.483 4.0 1.434 1.409 1.459 1.389 1.479 5.0 1.430 1.405 1.455 1.385 1.475 6.0 1.426 1.401 1.451 1.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 19. VCC Tolerances for the Mobile Intel Celeron Processor in the Deep Sleep State: VID = 1.45 V VCC (V) ICC (A) 34 Static Transient Typ Min Max Min Max 0.0 1.388 1.363 1.413 1.343 1.433 1.0 1.384 1.359 1.409 1.339 1.429 2.0 1.380 1.355 1.405 1.335 1.425 3.0 1.376 1.351 1.401 1.331 1.421 4.0 1.372 1.347 1.397 1.327 1.417 5.0 1.368 1.343 1.393 1.323 1.413 6.0 1.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 20. VCC Tolerances for the Mobile Intel Celeron Processor: VID = 1.50 V VCC (V) ICC (A) 298517-006 Static Transient Typ Min Max Min Max 0.0 1.50 1.475 1.525 1.455 1.545 1.0 1.496 1.471 1.521 1.451 1.541 2.0 1.492 1.467 1.517 1.447 1.537 3.0 1.488 1.463 1.513 1.443 1.533 4.0 1.484 1.459 1.509 1.439 1.529 5.0 1.480 1.455 1.505 1.435 1.525 6.0 1.476 1.451 1.501 1.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 21. VCC Tolerances for the Mobile Intel Celeron Processor in the Deep Sleep State: VID = 1.50 V VCC (V) ICC (A) 36 Static Transient Typ Min Max Min Max 0.0 1.438 1.413 1.463 1.393 1.483 1.0 1.434 1.409 1.459 1.389 1.479 2.0 1.430 1.405 1.455 1.385 1.475 3.0 1.426 1.401 1.451 1.381 1.471 4.0 1.422 1.397 1.447 1.377 1.467 5.0 1.418 1.393 1.443 1.373 1.463 6.0 1.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 5. Illustration of VCC Static and Transient Tolerances (VID = 1.15 V) 1.250 Transient Maximum Static Maximum 1.200 Static Typical 1.150 V C C 1.100 Static Minimum 1.050 Transient Minimum 1.000 0.950 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 ICC Figure 6. Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting = 1.15 V) 1.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 7. Illustration of VCC Static and Transient Tolerances (VID = 1.40 V) 1.500 Transient Maximum 1.450 Static Maximum 1.400 Static Typical Vcc (V) 1.350 1.300 Static Minimum Transient Minimum 1.250 1.200 9. 0 10 .0 11 .0 12 .0 13 .0 14 .0 15 .0 16 .0 17 .0 18 .0 19 .0 20 .0 21 .0 22 .0 23 .0 8. 0 7. 0 6. 0 5. 0 4. 0 3. 0 2. 0 1. 0 0. 0 1.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 8. Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting = 1.40 V) 1.430 Transient Maxim um Static Maxim um Static Typical 1.380 Vcc (V) 1.330 1.280 Transient Minim um Static Minim um 1.230 1.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 22. AGTL Signal Group DC Specifications Symbol Parameter Min Max VIL Input Low Voltage -0.15 VIH Input High Voltage VREF+0.2 VCCT VREF-0.2 VOH Output High Voltage — RON Output Low Drive Strength Unit Notes V V See VCCT,max in Table 11 — V See VCCT,max in Table 11 16.67 Ω Note 2 IL Leakage Current for Inputs, Outputs and I/Os 100 Note 1 µA NOTES: 1.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 24. CLKREF, APIC, TAP, CMOS, and Open-drain Signal Group DC Specifications Symbol VIL15 Parameter Min Input Low Voltage, 1.5 V CMOS Max –0.15 VCMOSREFmin – 300 mV 0.36 Unit Notes V VIL18 Input Low Voltage, 1.8 V CMOS –0.36 V Notes 1, 2 VIH15 Input High Voltage, 1.5 V CMOS VCMOSREFmax + 2.0 250 mV V Note 10 VIH15PICD Input High Voltage, 1.5 V PICD[1:0] VCMOSREFmax + 2.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet (Tj) in the range 0°C to 100°C unless otherwise noted. Tj must be less than or equal to 100°C (or the otherwise-noted given value) for all functional processor states. Table 25. System Bus Clock AC Specifications (Differential) 1 Symbol Parameter Min System Bus Frequency Typ Max 133 T1 BCLK Period – average 7.5 T1abs BCLK Period – Instantaneous minimum 7.3 Unit Figure Notes MHz 7.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 26. System Bus Clock AC Specifications (133 MHz, Single Ended) 1 Symbol Parameter Min System Bus Frequency Max Unit 133 Figure Notes MHz T1S BCLK Period 7.5 7.65 ns ±250 ps 6 Note 2 T1Sabs BCLK Period – Instantaneous Minimum 7.25 T2S BCLK Period Stability T3S BCLK High Time 1.4 ns 6 at>2.0 V T4S BCLK Low Time 1.4 ns 6 at<0.5 V T5S BCLK Rise Time 0.4 ns 6 Note 5 Note 2 1.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 28. Valid Mobile Intel Celeron Processor Frequencies BCLK Frequency (MHz) Frequency Multiplier Core Frequency (MHz) Power-on Configuration bits [27,25:22] 100 6.5 650 0, 1111 133 5.5 733 0, 0100 133 7.5 1000 0, 1101 133 8 1066 133 8.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 29. AGTL Signal Groups AC Specifications1 2 RTT = 56Ω internally terminated to VCCT; VREF = /3VCCT; load = 50 ohms Symbol Parameter T7 AGTL Output Valid Delay T8 AGTL Input Setup Time Min 0.40 Max 3.25 0.95 Unit Figure ns 9 ns 10 1.30 T9 AGTL Input Hold Time 1 Notes Notes 2, 3, 6 Note 7 ns 10 Note 4 T10 RESET# Pulse Width 1 ms 11,12 Note 5 NOTES: 1.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 31.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 32. APIC Bus Signal AC Specifications 1 Symbol Parameter Min Max Unit T21 PICCLK Frequency 2 33.3 MHz T22 PICCLK Period 30 500 ns Figure Notes Note 2 6 T23 PICCLK High Time 10.5 ns 6 at>1.6 V T24 PICCLK Low Time 10.5 ns 6 at<0.4 V T25 PICCLK Rise Time 0.25 3.0 ns 6 (0.4 V – 1.6 V) T26 PICCLK Fall Time 0.25 3.0 T27 PICD[1:0] Setup Time 8.0 T28 PICD[1:0] Hold Time 2.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 33. TAP Signal AC Specifications1 Symbol Parameter Min Max Unit T30 TCK Frequency — 16.67 MHz T31 TCK Period 60 — T32 TCK High Time T33 TCK Low Time T34 TCK Rise Time Figure Notes ns 6 25.0 ns 6 25.0 ns 6 ≤ VCMOSREF-0.2V, Note 2 ns 6 (VCMOSREF-0.2V) – 5.0 ≥ VCMOSREF+0.2V, Note 2 (VCMOSREF+0.2V), Notes 2, 3 T35 TCK Fall Time 5.0 ns 6 (VCMOSREF+0.2V) – (VCMOSREF-0.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 9. BCLK (Single Ended)/PICCLK/TCK Generic Clock Timing Waveform Th Tr VH CLK VTRIP VL Tf Tl Tp D0003-01 NOTES: Tr=T5S, T5S1, T34, T25 (Rise Time) Tf=T6S, T6S1, T35, T26 (Fall Time) Th=T3S, T3S1, T32, T23 (High Time) Tl=T4S, T4S1, T33, T24 (Low Time) Tp=T1S, T1S1, T31, T22 (Period) VTRIP=1.25V for BCLK (Single Ended);1.0V for PICCLK; 1.0V for TCK VL=0.5V for BCLK (Single Ended);0.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 11. BCLK/BCLK# Waveform (Differential Mode) T1 VIH_DIFF V4 0V V5 VIl_DIFF T5 T6 Figure 12. Valid Delay Timings CLK Vc Vc TX Signal Tx V Valid Valid TPW D0004-00 NOTES: Tx = T7, T11, T29 (Valid Delay) Tpw = T14, T14B (Pulse Width) V = VREF for AGTL signal group; 1.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 13. Setup and Hold Timings Vc CLK Ts Th V Valid Signal D0005-00 NOTES: Ts = T8, T27 (Setup Time) Th = T9, T28 (Hold Time) V = VREF for AGTL signals; 1.0V for CMOS, APIC, and TAP signals Vc = Crossing point of BCLK rising edge and BCLK# falling edge for BCLK references (Differential Clock) = 1.25V (Single Ended Clock) Figure 14.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 15.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 16.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 17.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 18.Test Timings (Boundary Scan) TCK Tv Tw 0.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 20.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 21.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet 4. System Signal Simulations Systems must be simulated using IBIS models to determine if they are compliant with this specification. All references to BCLK signal quality also apply to BCLK# for Differential Clocking. 4.1 System Bus Clock (BCLK) and PICCLK DC Specifications and AC Signal Quality Specifications Table 35.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 37. PICCLK DC Specifications and AC Signal Quality Specifications Symbol Parameter Min Max Unit 0.4 Figure Notes V1 VIL20 V 20 Note 1 V2 VIH20 1.6 V 20 Note 1 V3 VIN Absolute Voltage Range -0.5 2.4 V 20 Undershoot, Overshoot, Note 2 V4 PICCLK Rising Edge Ringback 1.6 V 20 Absolute Value, Note 3 V5 PICCLK Falling Edge Ringback 0.4 V 20 Absolute Value, Note 3 NOTES: 1.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet 4.2 AGTL AC Signal Quality Specifications Ringback specifications for the AGTL signals are as follows: Ringback below VREF,max + 200 mV is not authorized during low to high transitions. Ringback above VREF,min – 200 mV is not authorized during high to low transitions. Overshoot and undershoot specifications are documented in Table 38 and Table 39 and illustrated in Figure 23. Figure 23.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 38. 133-MHz AGTL Signal Group Overshoot/Undershoot Tolerance at the Processor Core Max VCCT + Overshoot/Undershoot Magnitude (volts) Allowed Pulse Duration (ns) [Tj=100C (see Note 7)] Activity Factor = 0.01 Activity Factor = 0.1 Activity Factor = 1 1.78 1.5 0.15 0.015 1.73 3.5 0.35 0.035 1.68 7.2 0.72 0.072 1.63 15 1.5 0.15 1.58 15 3.2 0.32 1.53 15 6.5 0.65 1.48 15 14 1.40 NOTES: 1.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 40. Non-AGTL Signal Group Overshoot/Undershoot Tolerance at the Processor Core Max VCmos + Overshoot/Undershoot Magnitude (volts) Allowed Pulse Duration (ns) [Tj=100C (see note 6)] Activity Factor = 0.01 Activity Factor = 0.1 Activity Factor = 1 0.065 2.38 6.5 0.65 2.33 13 1.3 0.13 2.28 29 2.9 0.29 2.23 60 6 0.6 2.18 60 12 1.2 2.13 60 26 2.6 2.08 60 56 5.6 NOTES: 1.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet 4.3.1.2 VTTPWRGD Transition Parameter Recommendation Table 42. VTTPWRGD Transition Parameter Recommendation Parameter Recommendation Transition time (300 mV to 900 mV) Less than or equal to 100 µs In addition, the VTT_PWRGD signal should have reasonable transition time through the transition region. A sharp edge on the signal transition will minimize the chance of noise causing a glitch on this signal.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 24.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet 5. Mechanical Specifications 5.1 Socketable Micro-FCPGA Package The Mobile Intel Celeron Processor is packaged in a 478-pin Micro-FCPGA package. The Low Voltage and Ultra Low Voltage processors will not be available in this package. The mechanical specifications for the socketable package are provided in Table 43. Figure 25 through Figure 27 illustrate different views of the package. Table 43.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 25.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 26. Socketable Micro-FCPGA Package - Top and Side View SUBSTRATE KEEPOUT ZONE DO NOT CONTACT PACKAGE INSIDE THIS LINE 7 (K1) 8 places 5 (K) 4 places A 1.25 MAX (A3) D1 35 (D) Ø 0.32 (B) 478 places E1 35 (E) A2 PIN A1 CORNER 2.03 ± 0.08 (A1) NOTE: All dimensions in millimeters. Values shown are for reference only.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 27. Socketable Micro-FCPGA Package - Bottom View 14 (K3) AF AD AB Y V T P M K H F D B AE AC AA W U R 14 (K3) N L J G E C A 1 25X 1.27 (e) 3 2 5 4 7 6 9 8 10 11 13 15 17 19 21 23 25 12 14 16 18 20 22 24 26 25X 1.27 (e) NOTE : All dimensions in millimeters. Values shown are for reference only. See Table 36 for specific details.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet 5.2 Surface Mount Micro-FCBGA Package The Mobile Intel Celeron Processor will also be available in a surface mount, 479-ball Micro-FCBGA package. The Low Voltage and Ultra Low Voltage processors will be available only in this package. The Mobile Intel Celeron processors at 1.45V and 1.5V will not be available in this package. Mechanical specifications are shown in Table 44.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 28.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 29. Micro-FCBGA Package – Top and Side Views SUBSTRATE KEEPOUT ZONE DO NOT CONTACT PACKAGE INSIDE THIS LINE 7 (K1) 8 places 5 (K) 4 places 0.20 A A2 D1 35 (D) Ø 0.78 (b) 479 places E1 35 (E) K2 PIN A1 CORNER NOTE: All dimensions in millimeters. Values shown are for reference only. See Table 37 for specific details.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 30. Micro-FCBGA Package - Bottom View 1.625 (S) 4 places AF AD AB Y V T P M K H F D B AE AC 1.625 (S) 4 places AA W U R N L J G E C A 1 25X 1.27 (e) 3 2 5 4 7 6 9 8 10 11 13 15 17 19 21 23 25 12 14 16 18 20 22 24 26 25X 1.27 (e) NOTE: All dimensions in millimeters. Values shown are for reference only. See Table 37 for specific details.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet 5.3 Signal Listings Figure 31 is a top-side view of the ball or pin map of the Mobile Intel Celeron Processor with the voltage balls/pins called out. Table 45 lists the signals in ball/pin number order. Table 46 lists the signals in signal name order. Figure 31.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 45. Signal Listing in Order by Pin/Ball Number No. 74 Signal Name No. Signal Name No. Signal Name No.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet No. 298517-006 Signal Name G25 VSS G26 H1 No. Signal Name No. P23 Signal Name VSS No.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet No. AA7 76 Signal Name No. Signal Name No. Signal Name No.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 46. Signal Listing in Order by Signal Name No. 298517-006 Signal Name Signal Buffer Type No.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet No. H25 78 Signal Name D29# Signal Buffer Type AGTL I/O No. AF24 Signal Name DEP4# Signal Buffer Type AGTL I/O C26 D30# AGTL I/O AD26 DEP5# AGTL I/O K24 D31# AGTL I/O AC26 DEP6# AGTL I/O G26 D32# AGTL I/O AD24 DEP7# AGTL I/O K25 D33# AGTL I/O Y1 DRDY# AGTL I/O J24 D34# AGTL I/O AF8 DPSLP# 1.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet No. AD10 Signal Name Signal Buffer Type No. Signal Name Signal Buffer Type TCK 1.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet 6. VCC Thermal Specifications In order to achieve proper cooling of the processor, a thermal solution (e.g., heat spreader, heat pipe, or other heat transfer system) must make firm contact to the exposed processor die. The processor die must be clean before the thermal solution is attached or the processor may be damaged.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 48. Power Specifications for Mobile Intel Celeron Processor Symbol Core Frequency/Voltage Thermal Design Power TDP W 650 MHz & 1.10 V 700 MHz & 1.10 V 733 MHz & 1.10 V 800 MHz & 1.10V 650 MHz & 1.15 V 733 MHz & 1.15 V 866 MHz & 1.15 V 1.000 GHz & 1.40 V 1.266 GHz & 1.40 V 1.066 GHz & 1.45 V 1.133 GHz & 1.45 V 1.200 GHz & 1.45 V 1.333 GHz & 1.50 V Symbol Unit 7.0 7.0 7.0 7.0 10.6 11.2 9.61 22.0 22.0 23.2 23.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet 6.1 Thermal Diode The Mobile Intel Celeron Processor has an on-die thermal diode that should be used to monitor the die temperature (TJ). A thermal sensor located on the motherboard, or a stand-alone measurement kit, should monitor the die temperature of the processor for thermal management or instrumentation purposes. Table 49 and Table 50 provide the diode interface and specifications.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet 7. Processor Initialization and Configuration 7.1 Description The Mobile Intel Celeron Processor has some configuration options that are determined by hardware and some that are determined by software. The processor samples its hardware configuration at reset on the active-to-inactive transition of RESET#. The P6 Family of Processors Developer’s Manual describes these configuration options.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet 8. Processor Interface 8.1 Alphabetical Signal Reference A[35:3]# (I/O – AGTL) The A[35:3]# (Address) signals define a 236-byte physical memory address space. When ADS# is active, these signals transmit the address of a transaction; when ADS# is inactive, these signals transmit transaction information. These signals must be connected to the appropriate pins/balls of both agents on the system bus.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet BCLK, BCLK# (I) The BCLK and BCLK# signals determines the system bus frequency. On systems with Differential Clocking, both system bus agents must receive these signals to drive their outputs and latch their inputs on the BCLK rising edge and BCLK# falling edge. All external timing parameters are specified with respect to the crossing point of the BCLK rising edge and BCLK# falling edge.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet BP[3:2]# (I/O - AGTL) The BP[3:2]# (Breakpoint) signals are the System Support group Breakpoint signals. They are outputs from the processor that indicate the status of breakpoints. BPM[1:0]# (I/O - AGTL) The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance monitor signals.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet a resistor divider to generate 1.25 V from the 2.5-V supply. A minimum of 1-µF decoupling capacitance is recommended on CLKREF. On systems with Differential Clocking, the CLKREF pin functions as the BCLK# input. CMOSREF (Analog) The CMOSREF (CMOS Reference Voltage) signal provides a DC level reference voltage for the CMOS input buffers. CMOSREF must be generated from a stable 1.5V supply (830 chipset family), 2.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet EDGCTRLP (I-Analog) The EDGCTRLP (Edge Rate Control) signal is used to configure the edge rate of the AGTL output buffers. Connect the signal to VSS with a 110-Ω, 1% resistor. FERR# (O - 1.5 V Tolerant Open-drain) The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked floatingpoint error.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet INTR (I - 1.5 V Tolerant) The INTR (Interrupt) signal indicates that an external interrupt has been generated. INTR becomes the LINT0 signal when the APIC is enabled. The interrupt is maskable using the IF bit in the EFLAGS register. If the IF bit is set, the processor vectors to the interrupt handler after completing the current instruction execution.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet PICD[1:0] (I/O - 1.5 V Tolerant Open-drain) The PICD[1:0] (APIC Data) signals are used for bi-directional serial message passing on the APIC bus. They must be connected to the appropriate pins/balls of all APIC bus agents, including the processor and the system logic or I/O APIC components.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet A number of bus signals are sampled at the active-to-inactive transition of RESET# for the power-on configuration. The configuration options are described in Section 4 and in the P6 Family of Processors Developer’s Manual.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet other conditions in are met, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no affect on the bus clock. TCK (I - 1.5 V Tolerant) The TCK (Test Clock) signal provides the clock input for the test bus (also known as the test access port). TDI (I - 1.5 V Tolerant) The TDI (Test Data In) signal transfers serial test data to the processor.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet VID[4:0] (O – Open-drain) The VID[4:0] (Voltage ID) pins/balls can be used to support automatic selection of power supply voltages. Please refer to Section 3.2.3 for details. VREF (Analog) The VREF (AGTL Reference Voltage) signal provides a DC level reference voltage for the AGTL input buffers. A voltage divider should be used to divide VCCT by 2/3. Resistor values of 1.00 kΩ and 2.00 kΩ are recommended.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet 8.2 Signal Summaries Table 52.
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 54.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Appendix A. PLL RLC Filter Specification A1. Introduction All Mobile Intel Celeron Processors have internal PLL clock generators, which are analog in nature and require quiet power supplies for minimum jitter. Jitter is detrimental to a system; it degrades external I/O timings as well as internal core timings (i.e. maximum frequency).
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Mobile Intel® Celeron® Processor (0.13 µ) Micro-FCBGA and Micro-FCPGA Packages Datasheet Figure 32. PLL Filter Specifications 0.2 dB 0 dB x dB Forbidden zone -28 dB Forbidden zone -34 dB DC 1 Hz fpeak 1 MHz 66 MHz Passband fcore High Frequency Band x = 20.log[(Vcct-60 mV)/ Vcct] NOTES: Diagram is not to scale No specification for frequencies beyond fcore. Fpeak, if existent, should be less than 0.05 MHz. A3. Recommendation for Mobile Systems The following LC components are recommended.
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Mobile Intel® Celeron® Processor (0.13 µ) in Micro-FCBGA and Micro-FCPGA Packages Datasheet Table 58. PLL Filter Resistor Recommendations Resistor Part Number Value Tolerance Power R1 Various 1Ω 10% 1/16W To satisfy damping requirements, total series resistance in the filter (from VCCT to the top plate of the capacitor) must be at least 0.35 Ω. This resistor can be in the form of a discrete component, or routing, or both. For example, if the picked inductor has minimum DCR of 0.